Smart testing at high temperatures
The ATHIS project focused on developing new methods for innovative, integrated, miniaturised and distributed electronic systems with reliable operation under high-temperature conditions (higher than 200°C). The high temperature electronic components and systems are aimed for further deployment in critical situations found within the automotive, aerospace, avionics, ship and oil extraction industries. Part of the project work involved the development of a testing scheme for a range of sub-circuits realised on 'System on Chip' (SoC) technology at temperatures around 250-300°C. The so-called 'Built Off-Chip Self Test' (BOST) has been included in a tester/oven interface. It provides suitable strategies for testing embedded memories in SoCs. A few examples of these memories include Static Random Access Memory (SRAM), Dual-Ported Random Access Memory (DPRAM) and Electrically Erasable Programmable Read-Only Memory (EEPROM). With the aid of programmable function blocks the test scheme features increased flexibility to test stimuli and high adaptability to accommodate changes in test algorithms. The key test algorithm used is the industrially known MARCH Test that is capable of detecting various types of faults. Such faults include all address, stuck-at, transition and coupling faults under varied complexity of the memory array architecture. Moreover, the algorithm has the potential to test Word Oriented Memories (WOM) through substitution of the bit read/write commands by word operations. Other possible system capabilities include circuitry fault detection in cases where common voltage test methods fail to describe properly. The system can find useful applications in a wide range of test scenarios, including failure mode analysis and reliability testing. Its increased flexibility and low cost design make this system suitable for use by companies involved with the manufacture or use of high temperature electronic devices and systems.
