Project description
Open-source multicore processor for safety-critical applications receives commercial boost
RISC-V is a free and open-source hardware instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. The EU-funded De-RISC project aims to commercialise a multicore RISC-V system-on-a-chip design already developed by one project partner. The hardware development will be enhanced by enabling a safety-critical hypervisor (system software that guarantees non-interference between critical applications running over the same platform) to run in the project platform. The platform design takes into account multicore interference mitigation issues which are imperative for safety- and security-critical systems. It also has the potential to be implemented in field-programmable gate arrays and application-specific standard products. Importantly, there will be no imposed US export controls over the processor or the software. The project targets the use of the multicore RISC-V system-on-a-chip in safety-critical computers used in the space and the aviation fields.
Objective
The De-RISC project addresses computer systems within the space and aviation domains. De-RISC – Dependable Real-time Infrastructure for Safety-critical Computer – is a proposed project where an international consortium will introduce a hardware and software platform based around the RISC-V ISA. The work proposed in this project is to productize a multi-core RISC-V system-on-chip design already owned by CG and to port the XtratuM hypervisor owned by FEN to that design to create a full platform consisting of hardware and software for future European developments within space and aeronautical applications.
De-RISC brings critical features to the market that make it unique in front of the competition:
(1) No US export restrictions: most existing products use US technology, thus subject to US export control. De-RISC’s IP core platform and software will not be subject to any US regulatory influence by building on RISC-V.
(2) Multi-core interference mitigation concepts by BSC integrated in the RISC-V SoC and validated by TRT become a unique feature, and will provide a key advantage w.r.t. competitors by limiting drastically interference while preserving high-performance operation.
(3) Portability: The proposed development will create a RISC-V HW/SW platform that can be implemented in FPGAs and application specific standard products. This provides an edge for integrators that can adapt their choice of implementation technology based on mission requirements.
(4) Fault-tolerance concepts: The platform will be provided by companies with experience in the space domain and with heritage in design of fault-tolerant systems.
(5) Future-proof selection for new platforms: New software products are not being ported to SPARC and PowerPC architectures. With an established vendor providing a RISC-V platform there are guarantees of continued support for the hardware platform while developments from the commercial domain for the RISC-V architecture can be leveraged over time.
Fields of science
Programme(s)
Funding Scheme
IA - Innovation actionCoordinator
46022 Valencia
Spain
The organization defined itself as SME (small and medium-sized enterprise) at the time the Grant Agreement was signed.