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Content archived on 2024-05-27

Nanoresonators with Integrated circuitry for high sensitivity and high resolution mass detection

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Mass-sensing nano-cantilevers on a chip

As miniaturisation of cantilever dimensions increases both the mass and spatial resolution of resonating cantilever-based mass sensors, a dedicated fabrication method for nanometre-sized cantilevers has been introduced.

Mass detection is based on monitoring the resonant frequency shift when nanometre-sized particles are deposited on cantilevers, electronically excited by an electrode located at submillimetre distance. However, the magnitude of the current to be detected is proportional to the coupling capacitance between the cantilever and the driver. To eliminate the parasitic capacitance introduced by external bonding pads and wires, silicon cantilevers resonators were monolithically integrated with CMOS (Complementary Metal Oxide Semiconductor) signal conditioning circuits. In particular, the NANOMASS II project has developed the methodology to combine standard CMOS technology with nanofabrication techniques of resonant cantilevers. More specifically, at the laboratories of Technical University of Denmark, nano-cantilevers were integrated with CMOS circuitry by post-processing a CMOS chip. Local openings were created in the top passivation layer of the CMOS and the upper poly-silicon layer was etched down to the 100nm thin thermal oxide. The next step was to deposit a thin aluminium (Al) layer on the oxide, which was then used as an etch mask to transfer the cantilever structure to the lower poly-silicon layer of the CMOS. To define the cantilever pattern, low-energy electron beam lithography was combined with direct-write laser lithography (DWL), which could lead to significant reductions in the fabrication costs. Before releasing the cantilever in buffered hydrofluoric acid (BHF), a supportive photoresist coating was applied and an opening was created over the fabricated structures to eliminate static friction. The cantilevers with dimensions approaching the grain size of the poly-silicon are finally dry-released after oxygen plasma ashing. Optimisation of the poly-silicon grain size was attempted by the NANOMASS II project partners, but it was not possible to improve the structure further due to CMOS processing limitations. Further miniaturisation will be based on alternative materials for the cantilever, such as amorphous metals or single crystal silicon.

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