Beyond the CMOS scaling limit
Single-electron memory (SEM) devices are offering an attractive solution to the technological problems arising while approaching the CMOS (complementary metal-oxide semiconductor) scaling limit. Consisting of a nano-floating gate on a narrow channel MOSFET (metal-oxide semiconductor field-effect transistor), they are still based on the conventional concept of 'charge transfer'. Not only compatibility with conventional CMOS technology is therefore ensured, but re-using the huge amount of know-how accumulated could address existing power dissipation problems. The technology proposed by the SASEM project relies on implantation of arsenic (As) to create a Gaussian profile of impurities in the active layer of a silicon-on-insulator (SOI) wafer. After defining the silicon mesa by lithography and dry etching, wet oxidation was performed to separate it into two wires with silicon oxide in between. The oxidation rate was increased in the presence of arsenic, while the variability of the silicon mesa width enabled the creation of a quantum dot on top of the continuous triangular channel. The quantum dot was charged/discharged by applying a negative/positive voltage to the gate respectively and the induced change in drain current was used for readout. To ensure efficient control of the formation and size of the nano-floating gate, the entire device fabrication process was thoroughly investigated and simulated using the most reliable models. Critical process parameters such as oxidation temperature and time were subsequently optimised, as well as reproducibility guaranteed. The fabricated single-electron device has been tested for memory operations at room temperature and the estimated performance characteristics are comparable to those of existing devices. While improvements are needed before the technology's industrial implementation, the feasibility of the device's down-scaling was shown and the use of quantum effects in practical devices has been brought closer.
