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At the nano-scale, process simulation becomes crucial to obtain accurate (sub-nm resolutions) device size that are sometimes hardly measurable. In this respect, existing tools provide widespread performances that depend on the specific problem to solve. Some are good tools for implantation, others are better for oxidation.
Our first objective was thus to evaluate performances regarding our specific device, and in particular wet and dry oxidation. Moreover, we wanted to deliver a simulation tool that would optimize device size and process parameters to obtain the most reliable process. This was done thanks to the collaboration between IEMN and UCL. IEMN developed the tools, and UCL performed the test processes and characterization.
At the end we have a process simulation tool that is accurate enough to predict sub-nm Si dot sizes in an embedded gate oxide, which is an important result for the development of any nano-memory device.
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