Quantum Tunneling Device Technology on Silicon

The speed-index is a quality means of electronic switching devices. A high current is needed to switch the capacitive load from one logic level to the other. All ITD devices of sample S1408 with an emitter area between 10µm² and 30µm² exhibit a speed index of <1ns/V. E.Khorenko, W.Prost, F.J.Tegude, M.Stoffel, R.Duschl, M.W.Dashiell, O.G.Schmidt, G. Klimeck; Manufacturability and Electrical Characteristics of Si/SiGe Interband Tunnelling Diodes, Proc. 5th Int. Conf. on Advanced Semiconductor Devices and Microsystems, IEEE Cat. No. 04EX867, ISBN 0-7803-8535-7, pp. 29 32, Smolenice, Slovakia, 17-21 October 2004. (KB).

An assessment was carried out to determine the potential of RTD based circuit topologies in VLSI architecture such as an FPGA, which is often used as a means of implementing neural networks. This particular application was chosen as it demonstrates very well the important issues facing VLSI chips such as: the drive to maintain (in line with Moores law) functional density/capacity, the high proportion of metal to device area due to interconnection conductors, propagation delay and power consumption. The core functionality of FPGAs is derived from SRAM based LUTs whilst the architecture can be configured for different application domains.

A MOBILE circuit and a threshold logic gate based on a Si/SiGe ITD and MODFET were simulated in HSPICE. The results demonstrated correct operation for both the MOBILE and the TLG. For the device chosen the resulting circuit required positive and negative going input signals to modulate the current in the MODFET sufficiently to produce MOBILE operation. The simulations also showed that it would be necessary to include level shifting circuitry if this signal system was chosen. P.M. Kelly, C.J. Thompson, T.M. McGinnity, and L.P. Maguire, Investigation of a Programmable Threshold Logic Gate Array IEEE International Conference Electronics Circuits and Systems, proceedings Vol. II, pp 673-67, Sept 2002.

Two objectives have been focussed in this period: a deeper knowledge of the self-latching feature in MOBILE-based circuits and the development of circuit topologies able to implement generalized threshold logic functions, i.e., Multi-threshold Threshold Gates (MTTGs). - M.J. Avedillo, J.M. Quintana, H. Petthengui, P. Kelly, C.J.Thomson; Multi-threshold Threshold Logic Circuit Design Using Resonant Tunneling Devices, Electronics Lett., 39, no. 21, pp. 1502-1503, 2003. - H. Pettenghi, M.J. Avedillo, and J.M. Quintana, A CAD tool for the design of RTD programmable gates based on MOBILE, Proc. Design of Circuits and Integrated Systems Conf. (DCIS'04), pp. 25-30, 2004.

Negative differential resistance has been obtained from a number of devices from a Daimler Chrysler resonant tunnelling diode wafer at 77 K. A peak current density of 14.9 A/cm² with a peak-to-valley current ratio of 2.1 achieved. Work is still progressing to try to improve on the performance of the RTDs. - P. See and D.J. Paul, The scaled performance of Si/Si1-xGex resonant tunnelling diodes IEEE Elec. Dev. Lett. 22, 582 (2001). - D.J. Paul et al., Si/SiGe electron resonant tunnelling diodes Appl. Phys. Lett. 77, 1653 (2000).

The functional capability of the Multi-Threshold Neuron circuit topology is evaluated. Two improvements have been made to it. First, it has been shown that two-output neurons can be realized through suitable sizing of RTDs. Second, the circuit topology has been extended to implement programmable neurons. A design methodology has been developed which systematize the design of complex neurons with RTDs. Extremely compact implementations of useful logic blocks have been produced as an application.

At the initial stages of the project threshold logic gates and circuits were designed and simulated using models of III/V based RTDS and HFETs. These displayed high speed but were limited in fan-in and fan-out capabilities and as a result were unlikely to be viable at large scale integration. By contrast the circuits simulated for Si/SiGe based ITDs and NMOS/CMOS FETs showed a reduced speed but highly increased fan-in and fan-out. The models developed for the Si/SiGe ITD and high performance NMOSFET showed good correlation with the measured results and circuits

The room temperature I/V characteristic of the RTD on silicon substrate exhibits a Negative-Differential Resistance (NDR). This device is the first successful demonstration of an epitaxial III/V semiconductor RTDs on a silicon substrate. S.Neumann A.Bakin, W.Prost, H.-H.Wehmann, A.Schlachetzki, F.J.Tegude; Growth of III/V Resonant Tunnelling Diode on Si Substrate with LP-MOVPE, J Crystal Growth 248 (2003) 380-383. V.Khorenko, A.C.Mofor, A.Bakin, S.Neumann, A.Guttzeit, H.H.Wehmann, W.Prost, A.Schlachetzki, F.J.Tegude, Buffer Optimization for InP-on-Si (001) Quasi-Substrates, 16th InP & Related Materials Conference, Kagoshima City, Japan, May 31 to June 4, 2004.

A reprogrammable threshold logic gate capable of realising all possible binary functions for any number of inputs was designed and simulated. The design features an architecture based on the Davio Expansion which facilitates the increase from the initial 2 input programmable gate to any number of inputs. The gate is programmable using soft MVL weights which allows its functionality to be changed after manufacture thus making it suitable for inclusion VLSI devices such as FPGAs or other arrays suite to the implementation of neural networks.

A monolithically integrated MOBILE circuit with a pin-diode at the input and an output amplifier based on HFETs was designed. Functionality of the designed circuit was demonstrated using InP-based devices. InGaAs/InAlAs resonant-tunnelling diodes and Metal-Shottky-Metal diodes were successfully realized on Silicon substrate. Full realisation of the MOBILE using III/V-on-Si could not be achieved within the limits of this project because of the conductive layer at the interface between the Si substrate and the InP buffer parallel to the HFET channel.

The manufacturability of the Si/SiGe ITD has been studied intensively. For the diodes with 5um2 device area the standard deviation of the peak current was about 16 %. The homogeneity of the peak voltage depends on the homogeneity of the epitaxial growth. In this case even a one-nanometer difference in the layer thickness plays a critical role. For the presented structure a standard deviation of the peak voltage was about 15%. For the PVCR a standard deviation of 4% and 8% was obtained. The ITD fulfils all requirements except the reproducibility of the peak current density.

Si/SiGe quantum well based interband tunnelling diodes exhibiting high peak to valley current ratios (up to 5.6) have been realized using solid source molecular beam epitaxy (MBE) [1]. We report also the first room temperature demonstration of negative differential resistance in diodes incorporating self-assembled Ge quantum dots [2]. In that case, a detailed structural optimisation leads to peak to valley current ratios between 2 and 3 [3]. M. Stoffel, G. S. Kar, S. Kiravittaya, O. G. Schmidt, J. Appl. Phys. , submitted (2004) M. W. Dashiell, C. Müller, N. Y. Jin-Phillip, U. Denker, O. G. Schmidt, K. Eberl, Mat. Sci. Eng. B 89, 106 (2002) M. Stoffel, G. S. Kar, O. G. Schmidt, Mat. Sci. Eng. C, submitted (2004).

A report has been distributed to the partners detailing different integration schemes between Si-based tunnel diodes and Si transistors. The QUDOS partners will be attempting to fabricate an inverted strained-Si MODFET with an integrated Si/SiGe RTD produced with a single epitaxial growth. The best performing system for most tunnel diode circuits is the strained-Si CMOS technology with integrated RTDs.

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