Object-oriented co-design and functional test techniques

Informazioni relative al progetto

ODETTE

ID dell’accordo di sovvenzione: IST-1999-11476

Progetto chiuso

Data di avvio 2 Maggio 2000

Data di completamento 31 Luglio 2003

Finanziato da

• Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002"

Costo totale € 5 703 050,00

Contributo UE € 3 536 629,00

Coordinato da

KURATORIUM OFFIS E. V.
Germany

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Formalization of an enhanced design flow including OSSS synthesis, System C/VHDL co-simulation and CoCentric system studio environment for rapid FPGA prototyping

The formalization of the design flow that has been described in D1.5, is a SystemC"-based synthesis flow. It includes the OFFIS OSSS synthesis tool, Cocentric System Studio environment and finally the Xilinx flow to reach the FPGA implementation level. CoCentric System Studio provides as outputs synthesizable RTL hardware models in VHDL and Verilog and constitutes the link between the high-level-models in OSSS and the FPGA synthesis environment.� Regarding exploitation, this design flow can be partitioned in two parts: OSSS modelling (OFFIS synthesis tool) SystemC" modelling (Synopsys and Xilinx flows). The exploitation that we foresee for the former is based on a follow-up possibly IST research project that can implement the required enhancements and optimisations. Siemens MC is available for a continuation of these research activities, providing models in SystemC" Plus and SystemC and formalizing and using a design flow that includes synthesis (with Synopsys System Studio, or other behavioural synthesis tools that may be available on the market in future) and FPGA flow to reach the implementation stages and evaluate the final results of the design activity. The latter will be exploited internally under commercial agreements with Synopsys and Xilinx. In the next year, research projects internal to Siemens MC and in cooperation with consultants, such as Politecnico Milano and Cefriel, will make use of CoCentric System Studio for synthesis-based research activities connected to FPGA design flow. Moreover an agreement between Siemens MC, Synopsys and Xilinx is in place in Italy in order to exploit the synthesis flow for an innovative targeted platform belonging to the Xilinx Virtex-II Pro family. This family enables designers to implement embedded processor-based applications with large flexibility using also IP cores and customized modules.

OSSS (ODETTE System Synthesis Subset) - Simulation library (also called OOHWLIB)

The object-oriented design flow developed within the ODETTE project allows one to implemen embedded systems using the so-called ODETTE System Synthesis Subset (OSSS). This subset defines the language elements available for describing a synthesisable, i.e., processable by the ODETTE Synthesiser (c.f. result 1), model of an embedded system. Since the OSSS is based on SystemC/C++ it can be simulated using the standard SystemC simulation environment. The OSSS simulation library is a C++ library that needs to be included in an OSSS compliant simulation model. It defines the language elements syntactically and also their timing behaviour for a cycle-true simulation, thus guaranteeing the correct behaviour of the specified components.

Generic class library of design components (GCL)

In ODETTE a library called Generic Class Library (GCL) has been developed. It includes basic elements like storage elements (memories, FIFOs, Stacks), structures for computations (arrays, matrixes) and interfacing elements. This library is public and available on the ODETTE web site. The library has been developed using the syntax and guidelines of OSSS and are apt for being used in a synthesis environment that includes the OFFIS synthesis tool that generates the corresponding SystemC version of the models including the library cells. For a productive use the library require the OFFIS synthesis tool to be used, so their exploitation is dependent on the exploitation of this tool as is specified as result 1 in this document. Benefits of the approach include: Abstraction and re-use, key features for managing the complexity of designs. Both are applied in the library cells. Parameterisation allows reusing modules with different characteristics. All the library elements have been modelled exploiting this feature, including encapsulation due to the definition of the methods that are associated to the modules.

System C/VHDL co-simulation tool

The co-simulation interface developed in the workpackage 2 of the project uses the Synopsys SystemC" front-end also developed in the ODETTE project in the context of the Workpackage 1 (synthesis engine). The interface has been designed to accept a broad range of simulator interfaces and can thus work with different languages (VHDL Verilog) and commercial simulators. The co-simulator tool developed and evaluated in ODETTE is part of a much broader Synopsys product, Synopsys CoCentric System Studio. CoCentric System Studio is a SystemC" based design environment, including simulator and specification environment for the verification and analysis of algorithmic, architectural, hardware, and software models at multiple levels of abstraction. System Studio provides as outputs executable specifications of the design, simulation data, and synthesizable SystemC" RTL hardware models. Particularly, CoCentric SystemC" Compiler accepts behavioural and RTL SystemC" descriptions and generates gate-level netlists for rapid prototyping of FPGA or ASIC hardware. Further developments will be performed to improve the interface performances for large designs as well as improve the co-simulation between SystemC and SystemVerilog for Transaction Level Models (TLM).

ODETTE high-level synthesizer

Current state-of-the-art EDA (electronic design automation) tools support the design of electronic components at a rather low level of abstraction. Circuits need to be described at the so-called register transfer or behavioural level. In particular, these tools do not support any modern specification concepts such as the object-oriented paradigm. The ODETTE High-Level Synthesizer (OHLS) is a tool to translate high-level specifications which are based on a subset of the system design language SystemC into a representation processable by current industrial EDA tools. The above mentioned subset of SystemC contains language concepts that promise a higher productivity of components, an improved prospect for the reuse of so-called IP-components, and the ability to manage very complex systems which would not be possible with state-of-the art methods. By now the OHLS reached an advanced prototypic status. It has proven the concepts underlying the projects proposal. The tool has been used and evaluated extensively within the project by industrial partners in the consortium. Since it is based on a technology owned by another partner, it is yet not possible to commercially exploit the OHLS. From the current status we estimate that another 2 person-year of work would be necessary to make the OHLS a pre-product and independent tool.