Periodic Reporting for period 1 - NEoteRIC (NEuromorphic Reconfigurable Integrated photonic Circuits as artificial image processor)
Période du rapport: 2020-01-01 au 2021-06-30
NEoteRIC’s primary objective is the generation of holistic photonic machine learning paradigms that will address demanding imaging applications in an unconventional approach providing paramount frame rate increase, classification performance enhancement and orders of magnitude lower power consumption compared to the state-of-the-art machine learning approaches.
NEoteRIC’s implementation stratagem incorporates multiple innovations spanning from the photonic “transistor” level and extending up to the system architectural level, thus paving new, unconventional routes to neuromorphic performance enhancement.
The technological cornerstone of NEoteRIC relies on the development and upscaling of a highspeed reconfigurable photonic FPGA-like circuit that will incorporate highly dense and fully reconfigurable key silicon photonic components (ring resonators, MZIs, etc.). High-speed reconfigurability will unlock the ability to restructure the photonic components and rewire inter-component connections.
Through NEoteRIC the integrated photonic FPGAs will be strengthened by the incorporation of novel marginal-power consuming non-volatile high-speed phase shifters that will push the boundaries of energy consumption. NEoteRIC’s “unconventional” chips will be utilized as a proliferating neuromorphic computational platform that will merge the merits of photonic and electronic technology and will allow the all-optical implementation of powerful non-von Neumann architectures such as Reservoir Computing, Recurrent Neural Networks, Deep Neural Networks and Convolutional Neural Networks simultaneously by the same photonic chip.
NEoteRIC’s implementation stratagem incorporates multiple innovations spanning from the photonic “transistor” level and extending up to the system architectural level, thus paving new, unconventional routes to neuromorphic performance enhancement.
The technological cornerstone of NEoteRIC relies on the development and upscaling of a highspeed reconfigurable photonic FPGA-like circuit that will incorporate highly dense and fully reconfigurable key silicon photonic components (ring resonators, MZIs, etc.). High-speed reconfigurability will unlock the ability to restructure the photonic components and rewire inter-component connections.
Through NEoteRIC the integrated photonic FPGAs will be strengthened by the incorporation of novel marginal-power consuming non-volatile high-speed phase shifters that will push the boundaries of energy consumption. NEoteRIC’s “unconventional” chips will be utilized as a proliferating neuromorphic computational platform that will merge the merits of photonic and electronic technology and will allow the all-optical implementation of powerful non-von Neumann architectures such as Reservoir Computing, Recurrent Neural Networks, Deep Neural Networks and Convolutional Neural Networks simultaneously by the same photonic chip.
In the first 18 months, the NEoteRIC consortium achieved the following highlights:
-During this reporting period all design actions are according to plan allowing the successful implementation of the objective and this is solidified by the on-time delivery of all associated deliverables and milestones without any delays.
-Fabrication wise, several test BTO based test structures have been sent for fabrication so as to find the best parameters in terms of silicon waveguide geometry, BTO thickness and SiN waveguide geometry, according to the design guidelines mentioned above. These test circuits are now in fabrication. Up to this reporting period there are no significant deviations regarding BTO structures compared to the workplan in ANNEX I. Nonetheless, an alternative approach will be carved in order to mitigate near future delays. In particular generation 2 of reconfigurable devices will be based on thermo-optic phase shifters but with higher node count, whereas a proof-of-concept reconfigurable BTO based chip will be delivered at a “third” run, having few nodes.
-Realization of accurate numerical models that incorporate all the key physical features of the devices; meaning accurate dimensions and structures (hexagonal MZIs), laser source noise, noise at the detection, thermal crosstalk, parameter deviations due to low yield etc. These numerical models have been put into practice in order to emulate and evaluate different neural networks, among which, are vanilla RNNs, LSTMs, typical RC, new RC concepts, standard few layer FFNN and CNNs. Upcoming actions include the transfer of these concepts to the photonic chip.
In summary, the activities and achievements in the first period are according to the planned objectives and lay the ground, as planned, for NEoteRIC work in the second period. On the other hand, the SARS-COV2 pandemic has generated a delay in the fabrication related tasks due to the need for physical access to facilities under lockdown conditions. These changes are anticipated to significantly affect future progression and span over multiple WPs due to the strong inter-WP dependences.
-During this reporting period all design actions are according to plan allowing the successful implementation of the objective and this is solidified by the on-time delivery of all associated deliverables and milestones without any delays.
-Fabrication wise, several test BTO based test structures have been sent for fabrication so as to find the best parameters in terms of silicon waveguide geometry, BTO thickness and SiN waveguide geometry, according to the design guidelines mentioned above. These test circuits are now in fabrication. Up to this reporting period there are no significant deviations regarding BTO structures compared to the workplan in ANNEX I. Nonetheless, an alternative approach will be carved in order to mitigate near future delays. In particular generation 2 of reconfigurable devices will be based on thermo-optic phase shifters but with higher node count, whereas a proof-of-concept reconfigurable BTO based chip will be delivered at a “third” run, having few nodes.
-Realization of accurate numerical models that incorporate all the key physical features of the devices; meaning accurate dimensions and structures (hexagonal MZIs), laser source noise, noise at the detection, thermal crosstalk, parameter deviations due to low yield etc. These numerical models have been put into practice in order to emulate and evaluate different neural networks, among which, are vanilla RNNs, LSTMs, typical RC, new RC concepts, standard few layer FFNN and CNNs. Upcoming actions include the transfer of these concepts to the photonic chip.
In summary, the activities and achievements in the first period are according to the planned objectives and lay the ground, as planned, for NEoteRIC work in the second period. On the other hand, the SARS-COV2 pandemic has generated a delay in the fabrication related tasks due to the need for physical access to facilities under lockdown conditions. These changes are anticipated to significantly affect future progression and span over multiple WPs due to the strong inter-WP dependences.
The technological evolution of photonic FPGA technology within NEoteRIC will provide a multiplicative effect in the number of integrated units (4 times improvement), in the number of available I/O (2 times improvement) and a reduction of power consumption (5 times improvement). This advantage will render the scheme superior compared to previous photonic neuromorphic approaches in terms of node number, power consumption and operational bandwidth.
NEoteRIC’s BTO enhanced photonic FPGAs will unleash the potential for four orders of magnitude decrease in the energy consumption per unit, nanosecond reconfiguration capabilities and negligible power consumption per operation through BTO phase shifters. This feature will render NEoteRIC’s proposition superior to all processing electronic/photonic counterparts in terms of operational bandwidth/power consumption.
The generation of a high-performance photonic FPGA PICs will offer a proliferating platform for implementing a series of state-of-the-art machine learning paradigms directly in the optical domain.
The implementation of training techniques directly on-chip alleviating the need for offline training. NEoteRIC’s objective is to investigate and implement cutting edge training schemes such as Brute-force computation of gradient, Adjoint variable method and Nonlinearity Inversion. Through NEoteRIC’s photonic-FPGA a neuromorphic platform cytometric data analysis will be performed in the analogue-optical domain, alleviating the need for high-speed electronics, offering unparalleled speed, eliminating offline data storage and minimizing power consumption due to photonic passive processing.
The in-project excellence will be tested through demanding high impact application such as high frame-rate image analysis and in particular single-pixel time-stretch modalities thus pushing the boundaries of state-of-the-art; exhibiting simultaneous high spatial resolution and Gframe/sec processing rate.
NEoteRIC’s concept related to utilising analog neuromorphic processing for high-speed cytometry has already attracted the interest of key players in the market of medical imaging. Moreover, specific architectures of reconfigurable photonic chips suited for machine learning have already generated intellectual property in the form of a patent in the context of the project
NEoteRIC’s BTO enhanced photonic FPGAs will unleash the potential for four orders of magnitude decrease in the energy consumption per unit, nanosecond reconfiguration capabilities and negligible power consumption per operation through BTO phase shifters. This feature will render NEoteRIC’s proposition superior to all processing electronic/photonic counterparts in terms of operational bandwidth/power consumption.
The generation of a high-performance photonic FPGA PICs will offer a proliferating platform for implementing a series of state-of-the-art machine learning paradigms directly in the optical domain.
The implementation of training techniques directly on-chip alleviating the need for offline training. NEoteRIC’s objective is to investigate and implement cutting edge training schemes such as Brute-force computation of gradient, Adjoint variable method and Nonlinearity Inversion. Through NEoteRIC’s photonic-FPGA a neuromorphic platform cytometric data analysis will be performed in the analogue-optical domain, alleviating the need for high-speed electronics, offering unparalleled speed, eliminating offline data storage and minimizing power consumption due to photonic passive processing.
The in-project excellence will be tested through demanding high impact application such as high frame-rate image analysis and in particular single-pixel time-stretch modalities thus pushing the boundaries of state-of-the-art; exhibiting simultaneous high spatial resolution and Gframe/sec processing rate.
NEoteRIC’s concept related to utilising analog neuromorphic processing for high-speed cytometry has already attracted the interest of key players in the market of medical imaging. Moreover, specific architectures of reconfigurable photonic chips suited for machine learning have already generated intellectual property in the form of a patent in the context of the project