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Origami electronics for three dimensional integration of computational devices

Descrizione del progetto

Una nuova tecnologia di stacking 3D per ampliare la legge di Moore

La legge di Moore, la quale stabilisce che il numero di transistori che possono essere collocati in modo economico su un circuito integrato raddoppierà ogni 18 mesi, guida la progettazione dei transistor da oltre 50 anni. Tuttavia, la continua riduzione dei chip di silicio si avvicina a limiti fisici. Le nuove architetture di confezionamento, quali l’integrazione 3D (l’integrazione verticale dei chip), promettono da tempo di aumentare il numero di transistor. Il progetto ORIGENAL adotterà un approccio radicalmente nuovo per affrontare l’integrazione 3D ultradensa di chip. Alla base del concetto di confezionamento 3D di ORIGENAL c’è una tecnologia a transistore a film sottile costruita su un substrato a lamina sottile. L’architettura proposta consente lo stacking di migliaia di strati uno sopra l’altro, consentendo un’ulteriore miniaturizzazione per altri 30 anni.

Obiettivo

Increasing the integrated circuits complexity by lateral scaling, known as Moore’s law, was the major driving force for the semiconductor industry. Now, after more than 4 decades down scaling is approaching fundamental and also economic limitations, and new solutions for further increasing the transistor count are explored. Utilizing the third dimension in chip architecture is one of the most promising directions. However, current solutions like wafer-to-wafer stacking will only deliver solutions for the short term with maximum some tens of layers on-top of each other’s.
In the ORIGENAL project we propose a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices by using a thin-film-transistor (TFT) technology on thin foil substrate and the subsequent topological folding in order to achieve a dense 3D packaging with completely new integration architectures. This radically new approach will enable the stacking of thousands of layers on top of each other’s, each containing state-of-the-art CMOS circuits and thus will provide enough fuel to further increase the transistor count on a chip according to Moore’s law for more than 30 years. In addition, new computing concepts like neuromorphic computing will significantly benefit from the highly interconnected architecture developed in this project.
The proposal focuses on the development of a suitable thin-film-transistor technology on ultrathin-foil, the 3D interconnect and architecture, and the required technology for high precision folding. Achieving the ambitious objectives requires an interdisciplinary approach including contributions from Material science, electrical engineering, mechanical engineering, biology, physics and chemistry.
The proposed forefront research will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.

Invito a presentare proposte

H2020-FETOPEN-2018-2020

Vedi altri progetti per questo bando

Bando secondario

H2020-FETOPEN-2018-2019-2020-01

Meccanismo di finanziamento

RIA - Research and Innovation action

Coordinatore

BERGISCHE UNIVERSITAET WUPPERTAL
Contribution nette de l'UE
€ 334 132,50
Indirizzo
GAUSS-STRASSE 20
42119 Wuppertal
Germania

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Regione
Nordrhein-Westfalen Düsseldorf Wuppertal, Kreisfreie Stadt
Tipo di attività
Higher or Secondary Education Establishments
Collegamenti
Costo totale
€ 334 132,50

Partecipanti (4)