Skip to main content
European Commission logo
français français
CORDIS - Résultats de la recherche de l’UE
CORDIS
CORDIS Web 30th anniversary CORDIS Web 30th anniversary

Computing Server Architecture with Joint Power and Cooling Integration at the Nanoscale

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Publications

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Auteurs: Loris Duch, Miguel Peon-Quiros, Pieter Weckx, Alexandre Levisse, Ruben Braojos, Francky Catthoor, David Atienza
Publié dans: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numéro 28/10, 2020, Page(s) 2122-2133, ISSN 1063-8210
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2020.3003471

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays

Auteurs: M. Alayan, E. Muhr, A. Levisse, M. Bocquet, M. Moreau, E. Nowak, G. Molas, E. Vianello, J. M. Portal
Publié dans: IEEE Transactions on Circuits and Systems II: Express Briefs, Numéro 66/5, 2019, Page(s) 748-752, ISSN 1549-7747
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsii.2019.2908967

COCKTAIL: Multi-Core Co-Optimization Framework With Proactive Reliability Management

Auteurs: Darong Huang, Ali Pahlevan, Marina Zapater, David Atienza
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, Page(s) 1-1, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2021.3058959

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

Auteurs: Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
Publié dans: IEEE Access, Numéro 8, 2020, Page(s) 109297-109308, ISSN 2169-3536
Éditeur: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.3000867

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Auteurs: Yasir Mahmood Qureshi, Jose Manuel Herruzo, Marina Zapater, Katzalin Olcoz, Sonia Gonzalez Navarro, Oscar Plata, David Atienza
Publié dans: IEEE Transactions on Computers, 2020, Page(s) 1-1, ISSN 0018-9340
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2020.3041402

Multi-Agent Reinforcement Learning for Hyperparameter Optimization of Convolutional Neural Networks

Auteurs: Arman Iranfar, Marina Zapater, David Atienza
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, Page(s) 1-1, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2021.3077193

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

Auteurs: Huang, Darong; Pahlevan, Ali; Costero, Luis; Zapater Sancho, Marina; Atienza Alonso, David
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Numéro 2022, 2022, ISSN 1937-4151
Éditeur: IEEE
DOI: 10.1109/tcad.2022.3158832

E2CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices

Auteurs: Flavio Ponzina, Miguel Peon, Andreas Burg, David Atienza
Publié dans: IEEE Transactions on Computers, 2021, Page(s) 1-1, ISSN 0018-9340
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2021.3061086

Gem5-X

Auteurs: Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, Katzalin Olcoz, David Atienza
Publié dans: ACM Transactions on Architecture and Code Optimization, Numéro 18/4, 2021, Page(s) 1-27, ISSN 1544-3566
Éditeur: Association for Computing Machinary, Inc.
DOI: 10.1145/3461662

TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip

Auteurs: Arman Iranfar, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, David Atienza
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numéro 37/8, 2018, Page(s) 1532-1545, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2017.2768417

Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers

Auteurs: Ali Pahlevan, Xiaoyu Qu, Marina Zapater, David Atienza
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numéro 37/8, 2018, Page(s) 1667-1680, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2017.2760517

Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers

Auteurs: Arman Iranfar, Marina Zapater, David Atienza
Publié dans: IEEE Transactions on Parallel and Distributed Systems, Numéro 29/10, 2018, Page(s) 2268-2281, ISSN 1045-9219
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2018.2827381

PowerCool: Simulation of Cooling and Powering of 3D MPSoCs with Integrated Flow Cell Arrays

Auteurs: Artem Aleksandrovich Andreev, Arvind Sridhar, Mohamed M. Sabry, Marina Zapater, Patrick Ruch, Bruno Michel, David Atienza
Publié dans: IEEE Transactions on Computers, Numéro 67/1, 2018, Page(s) 73-85, ISSN 0018-9340
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2017.2695179

MAGNETIC: Multi-Agent Machine Learning-Based Approach for Energy Efficient Dynamic Consolidation in Data Centers

Auteurs: Kawsar Haghshenas, Ali Pahlevan, Marina Zapater, Siamak Mohammadi, David Atienza
Publié dans: IEEE Transactions on Services Computing, Numéro 31 May 2019, 2019, Page(s) 1-1, ISSN 1939-1374
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tsc.2019.2919555

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

Auteurs: Benoit W. Denkinger, Flavio Ponzina, Soumya S. Basu, Andrea Bonetti, Szabolcs Balasi, Martino Ruggiero, Miguel Peon-Quiros, Davide Rossi, Andreas Burg, David Atienza
Publié dans: IEEE Design & Test, Numéro August 2019, 2019, Page(s) 1-1, ISSN 2168-2356
Éditeur: IEEE Computer Society
DOI: 10.1109/mdat.2019.2947282

An in-Cache Computing Architecture for Edge Devices

Auteurs: William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
Publié dans: IEEE Transactions on Computers, 2020, Page(s) 1-1, ISSN 0018-9340
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2020.2972528

Containergy—A Container-Based Energy and Performance Profiling Tool for Next Generation Workloads

Auteurs: Wellington Silva-de-Souza, Arman Iranfar, Anderson Bráulio, Marina Zapater, Samuel Xavier-de-Souza, Katzalin Olcoz, David Atienza
Publié dans: Energies, Numéro 13/9, 2020, Page(s) 2162, ISSN 1996-1073
Éditeur: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/en13092162

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Auteurs: Alexandre Levisse, Pierre-Emmanuel Gaillardon, Bastien Giraud, Ian O'Connor, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal
Publié dans: IEEE Transactions on Nanotechnology, Numéro 18, 2019, Page(s) 183-194, ISSN 1536-125X
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tnano.2018.2887140

3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models

Auteurs: Federico Terraneo, Alberto Leva, William Fornaciari, Marina Zapater, David Atienza
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, Page(s) 1-1, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2021.3074613

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

Auteurs: Najibi, Halima ; Levisse, Alexandre Sébastien Julien ; Ansaloni, Giovanni ; Zapater Sancho, Marina ; Miroslav Vasic ; Atienza Alonso, David
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Numéro 2022, 2022, ISSN 1937-4151
Éditeur: IEEE
DOI: 10.1109/tcad.2022.3168257

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

Auteurs: Luis Costero, Arman Iranfar, Marina Zapater, Francisco D. Igual, Katzalin Olcoz, David Atienza
Publié dans: IEEE Transactions on Parallel and Distributed Systems, Numéro 31/12, 2020, Page(s) 2834-2850, ISSN 1045-9219
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2020.3004735

Functionality Enhanced Memories for Edge-AI Embedded Systems

Auteurs: Alexandre Levisse, Marco Rios, W.-A. Simon, P.-E. Gaillardon, D. Atienza
Publié dans: 2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019, Page(s) 1-4, ISBN 978-1-7281-4431-3
Éditeur: IEEE
DOI: 10.1109/nvmts47818.2019.8986214

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Auteurs: Halima Najibi, Alexandre Levisse, Marina Zapater
Publié dans: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, Page(s) 1-6, ISBN 978-1-7281-2954-9
Éditeur: IEEE
DOI: 10.1109/islped.2019.8824895

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Auteurs: Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza ESL
Publié dans: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, Page(s) 181-186, ISBN 978-1-7281-4123-7
Éditeur: IEEE
DOI: 10.1109/asp-dac47756.2020.9045220

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Auteurs: Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza
Publié dans: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Page(s) 18-23, ISBN 978-1-7281-5775-7
Éditeur: IEEE
DOI: 10.1109/isvlsi49217.2020.00014

INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection

Auteurs: Ferretti, Lorenzo ; Ansaloni, Giovanni ; Marquis, Renaud ; Teijeiro, Tomas ; Ryvlin, Philippe ; Atienza, David ; Pozzi, Laura
Publié dans: Design Automation and Test in Europe Conference (DATE), Numéro 2022, 2022
Éditeur: IEEE/ACM

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

Auteurs: Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Publié dans: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, Page(s) 1881-1886, ISBN 978-3-9819263-5-4
Éditeur: IEEE
DOI: 10.23919/date51398.2021.9474233

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

Auteurs: Rios, Marco Antonio ; Ponzina, Flavio ; Ansaloni, Giovanni ; Levisse, Alexandre Sébastien Julien ; Atienza Alonso, David
Publié dans: Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Numéro 2022, 2022, ISBN 978-1-4503-9322-5
Éditeur: IEEE
DOI: 10.1145/3526241.3530351

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

Auteurs: Najibi, Halima ; Levisse, Alexandre Sébastien Julien ; Ansaloni, Giovanni ; Zapater Sancho, Marina ; Atienza Alonso, David
Publié dans: Great Lakes Symposium on VLSI (GLVLSI), Numéro 2022, 2022
Éditeur: IEEE
DOI: 10.1145/3526241.3530309

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Auteurs: Denkinger, Benoît Walter ; Peon Quiros, Miguel ; Konijnenburg, Mario ; Atienza Alonso, David ; Catthoor, Francky
Publié dans: Design Automation Conference (DAC), Numéro 2022, 2022
Éditeur: ACM/IEEE

Thermal characterization of next-generation workloads on heterogeneous MPSoCs

Auteurs: Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza
Publié dans: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Numéro July 17-20, 2017, 2017, Page(s) 286-291, ISBN 978-1-5386-3437-0
Éditeur: IEEE
DOI: 10.1109/samos.2017.8344642

Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?

Auteurs: Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza
Publié dans: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numéro March 22-29, 2018, 2018, Page(s) 147-152, ISBN 978-3-9819263-0-9
Éditeur: IEEE
DOI: 10.23919/date.2018.8341994

Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation

Auteurs: Arman Iranfar, Ali Pahlevan, Marina Zapater, Martin Zagar, Mario Kovac, David Atienza
Publié dans: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numéro March 22-29, 2018, 2018, Page(s) 949-954, ISBN 978-3-9819263-0-9
Éditeur: IEEE
DOI: 10.23919/date.2018.8342146

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

Auteurs: Arman Iranfar, William Andrew Simon, Marina Zapater, David Atienza
Publié dans: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Numéro May 27-30, 2018, 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Éditeur: IEEE
DOI: 10.1109/iscas.2018.8351785

Design of a Two-Phase Gravity-Driven Micro-Scale Thermosyphon Cooling System for High-Performance Computing Data Centers

Auteurs: Andre Seuret, Arman Iranfar, Marina Zapater, John Thome, David Atienza
Publié dans: 2018 17th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Numéro May 29 - June 1, 2018, 2018, Page(s) 587-595, ISBN 978-1-5386-1272-9
Éditeur: IEEE
DOI: 10.1109/itherm.2018.8419531

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

Auteurs: Artem Aleksandrovich Andreev, Fulya Kaplan, Marina Zapater, Ayse K. Coskun, David Atienza
Publié dans: 2018 IEEE International Symposium on Low Power Electronics and Design, Numéro July 23 - 25, 2018, 2018, Page(s) 60-65, ISBN 978-1-4503-5704-3
Éditeur: Association for Computing Machinery
DOI: 10.1145/3218603.3218606

A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers

Auteurs: Arman Iranfar, Wellington Silva De Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza
Publié dans: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numéro 6-9 October 2019, 2019, Page(s) 211-216, ISBN 978-1-7281-3915-9
Éditeur: IEEE
DOI: 10.1109/vlsi-soc.2019.8920309

Enhancing Two-Phase Cooling Efficiency through Thermal-Aware Workload Mapping for Power-Hungry Servers

Auteurs: Arman Iranfar, Ali Pahlevan, Marina Zapater, David Atienza
Publié dans: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numéro March 25-29, 2019, 2019, Page(s) 66-71, ISBN 978-3-9819263-2-3
Éditeur: IEEE
DOI: 10.23919/date.2019.8715033

MAMUT: Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video Transcoding

Auteurs: Luis Costero, Arman Iranfar, Marina Zapater, Francisco D. Igual, Katzalin Olcoz, David Atienza
Publié dans: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numéro March 25-29, 2019, 2019, Page(s) 558-563, ISBN 978-3-9819263-2-3
Éditeur: IEEE
DOI: 10.23919/date.2019.8715256

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

Auteurs: Marco Rios, William Simon, Alexandre Levisse, Marina Zapater, David Atienza
Publié dans: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numéro October 6-9, 2019, 2019, Page(s) 34-39, ISBN 978-1-7281-3915-9
Éditeur: IEEE
DOI: 10.1109/vlsi-soc.2019.8920317

A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture

Auteurs: William Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza
Publié dans: Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19, Numéro June 2-6, 2019, 2019, Page(s) 1-6, ISBN 9781-450367257
Éditeur: ACM Press
DOI: 10.1145/3316781.3317741

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Auteurs: Joao Vieira, Edouard Giacomin, Yasir Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
Publié dans: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numéro October 6-9, 2019, 2019, Page(s) 160-165, ISBN 978-1-7281-3915-9
Éditeur: IEEE
DOI: 10.1109/vlsi-soc.2019.8920343

A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers

Auteurs: Wellington Silva de Souza, Arman Iranfar, Anderson Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza
Publié dans: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numéro October 6-9, 2019, 2019, Page(s) 230-231, ISBN 978-1-7281-3915-9
Éditeur: IEEE
DOI: 10.1109/vlsi-soc.2019.8920379

BLADE - A BitLine Accelerator for Devices on the Edge

Auteurs: William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza
Publié dans: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19, Numéro May 9-11, 2019, 2019, Page(s) 207-212, ISBN 9781-450362528
Éditeur: ACM Press
DOI: 10.1145/3299874.3317979

Gem5-X: A Gem5-based System Level Simulation Framework to Optimize Many-core Platforms

Auteurs: Yasir Qureshi, William Andrew Simon, Marina Zapater, David Atienza and Katzalin Olcoz
Publié dans: High Performance Computing (HPC 2019), Numéro April 29 - May 2, 2019, 2019, Page(s) 20-31, ISBN 9781-510892545
Éditeur: Society for Modeling and Simulation International (SCS)
DOI: 10.22360/springsim.2019.hpc.008

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Auteurs: William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
Publié dans: 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020
Éditeur: IFIP/IEEE
DOI: 10.1109/vlsi-soc46417.2020.9344087

Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning

Auteurs: Arman Iranfar, Federico Terraneo, Gabor Csordas, Marina Zapater, William Fornaciari, David Atienza
Publié dans: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Page(s) 418-423, ISBN 978-3-9819263-4-7
Éditeur: IEEE
DOI: 10.23919/date48585.2020.9116510

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Auteurs: Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza
Publié dans: Proceedings of the 2020 on Great Lakes Symposium on VLSI, 2020, Page(s) 513-518, ISBN 9781450379441
Éditeur: ACM
DOI: 10.1145/3386263.3406923

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Auteurs: Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
Publié dans: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Numéro 11733, 2019, Page(s) 34-47, ISBN 978-3-030-27561-7
Éditeur: Springer International Publishing
DOI: 10.1007/978-3-030-27562-4_3

Droits de propriété intellectuelle

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Numéro de demande/publication: 20 2016866566
Date: 2020-05-05

Associativity-Agnostic In-Cache Computing Memory Architecture Optimized for Multiplication

Numéro de demande/publication: 20 2016866566
Date: 2020-05-05

Recherche de données OpenAIRE...

Une erreur s’est produite lors de la recherche de données OpenAIRE

Aucun résultat disponible