Computing Server Architecture with Joint Power and Cooling Integration at the Nanoscale

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Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays

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Wydawca: Institute of Electrical and Electronics Engineers
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COCKTAIL: Multi-Core Co-Optimization Framework With Proactive Reliability Management

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Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2021.3058959

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

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Opublikowane w: IEEE Access, Numer 8, 2020, Strona(/y) 109297-109308, ISSN 2169-3536
Wydawca: Institute of Electrical and Electronics Engineers Inc.
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Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

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Opublikowane w: IEEE Transactions on Computers, 2020, Strona(/y) 1-1, ISSN 0018-9340
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2020.3041402

Multi-Agent Reinforcement Learning for Hyperparameter Optimization of Convolutional Neural Networks

Autorzy: Arman Iranfar, Marina Zapater, David Atienza
Opublikowane w: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, Strona(/y) 1-1, ISSN 0278-0070
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2021.3077193

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

Autorzy: Huang, Darong; Pahlevan, Ali; Costero, Luis; Zapater Sancho, Marina; Atienza Alonso, David
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Wydawca: IEEE
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E2CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices

Autorzy: Flavio Ponzina, Miguel Peon, Andreas Burg, David Atienza
Opublikowane w: IEEE Transactions on Computers, 2021, Strona(/y) 1-1, ISSN 0018-9340
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2021.3061086

Gem5-X

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Opublikowane w: ACM Transactions on Architecture and Code Optimization, Numer 18/4, 2021, Strona(/y) 1-27, ISSN 1544-3566
Wydawca: Association for Computing Machinary, Inc.
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TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip

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Opublikowane w: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numer 37/8, 2018, Strona(/y) 1532-1545, ISSN 0278-0070
Wydawca: Institute of Electrical and Electronics Engineers
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Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers

Autorzy: Ali Pahlevan, Xiaoyu Qu, Marina Zapater, David Atienza
Opublikowane w: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numer 37/8, 2018, Strona(/y) 1667-1680, ISSN 0278-0070
Wydawca: Institute of Electrical and Electronics Engineers
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Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers

Autorzy: Arman Iranfar, Marina Zapater, David Atienza
Opublikowane w: IEEE Transactions on Parallel and Distributed Systems, Numer 29/10, 2018, Strona(/y) 2268-2281, ISSN 1045-9219
Wydawca: Institute of Electrical and Electronics Engineers
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PowerCool: Simulation of Cooling and Powering of 3D MPSoCs with Integrated Flow Cell Arrays

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Wydawca: Institute of Electrical and Electronics Engineers
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MAGNETIC: Multi-Agent Machine Learning-Based Approach for Energy Efficient Dynamic Consolidation in Data Centers

Autorzy: Kawsar Haghshenas, Ali Pahlevan, Marina Zapater, Siamak Mohammadi, David Atienza
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Wydawca: Institute of Electrical and Electronics Engineers
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Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

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Wydawca: IEEE Computer Society
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An in-Cache Computing Architecture for Edge Devices

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Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2020.2972528

Containergy—A Container-Based Energy and Performance Profiling Tool for Next Generation Workloads

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Wydawca: Multidisciplinary Digital Publishing Institute (MDPI)
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Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

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Wydawca: Institute of Electrical and Electronics Engineers
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3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models

Autorzy: Federico Terraneo, Alberto Leva, William Fornaciari, Marina Zapater, David Atienza
Opublikowane w: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, Strona(/y) 1-1, ISSN 0278-0070
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2021.3074613

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

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Wydawca: IEEE
DOI: 10.1109/tcad.2022.3168257

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

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Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2020.3004735

Functionality Enhanced Memories for Edge-AI Embedded Systems

Autorzy: Alexandre Levisse, Marco Rios, W.-A. Simon, P.-E. Gaillardon, D. Atienza
Opublikowane w: 2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019, Strona(/y) 1-4, ISBN 978-1-7281-4431-3
Wydawca: IEEE
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A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Autorzy: Halima Najibi, Alexandre Levisse, Marina Zapater
Opublikowane w: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, Strona(/y) 1-6, ISBN 978-1-7281-2954-9
Wydawca: IEEE
DOI: 10.1109/islped.2019.8824895

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Autorzy: Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza ESL
Opublikowane w: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, Strona(/y) 181-186, ISBN 978-1-7281-4123-7
Wydawca: IEEE
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Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Autorzy: Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza
Opublikowane w: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Strona(/y) 18-23, ISBN 978-1-7281-5775-7
Wydawca: IEEE
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INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection

Autorzy: Ferretti, Lorenzo ; Ansaloni, Giovanni ; Marquis, Renaud ; Teijeiro, Tomas ; Ryvlin, Philippe ; Atienza, David ; Pozzi, Laura
Opublikowane w: Design Automation and Test in Europe Conference (DATE), Numer 2022, 2022
Wydawca: IEEE/ACM

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

Autorzy: Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Opublikowane w: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, Strona(/y) 1881-1886, ISBN 978-3-9819263-5-4
Wydawca: IEEE
DOI: 10.23919/date51398.2021.9474233

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

Autorzy: Rios, Marco Antonio ; Ponzina, Flavio ; Ansaloni, Giovanni ; Levisse, Alexandre Sébastien Julien ; Atienza Alonso, David
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Wydawca: IEEE
DOI: 10.1145/3526241.3530351

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

Autorzy: Najibi, Halima ; Levisse, Alexandre Sébastien Julien ; Ansaloni, Giovanni ; Zapater Sancho, Marina ; Atienza Alonso, David
Opublikowane w: Great Lakes Symposium on VLSI (GLVLSI), Numer 2022, 2022
Wydawca: IEEE
DOI: 10.1145/3526241.3530309

VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

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Wydawca: ACM/IEEE

Thermal characterization of next-generation workloads on heterogeneous MPSoCs

Autorzy: Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza
Opublikowane w: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Numer July 17-20, 2017, 2017, Strona(/y) 286-291, ISBN 978-1-5386-3437-0
Wydawca: IEEE
DOI: 10.1109/samos.2017.8344642

Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?

Autorzy: Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza
Opublikowane w: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numer March 22-29, 2018, 2018, Strona(/y) 147-152, ISBN 978-3-9819263-0-9
Wydawca: IEEE
DOI: 10.23919/date.2018.8341994

Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation

Autorzy: Arman Iranfar, Ali Pahlevan, Marina Zapater, Martin Zagar, Mario Kovac, David Atienza
Opublikowane w: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numer March 22-29, 2018, 2018, Strona(/y) 949-954, ISBN 978-3-9819263-0-9
Wydawca: IEEE
DOI: 10.23919/date.2018.8342146

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

Autorzy: Arman Iranfar, William Andrew Simon, Marina Zapater, David Atienza
Opublikowane w: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Numer May 27-30, 2018, 2018, Strona(/y) 1-5, ISBN 978-1-5386-4881-0
Wydawca: IEEE
DOI: 10.1109/iscas.2018.8351785

Design of a Two-Phase Gravity-Driven Micro-Scale Thermosyphon Cooling System for High-Performance Computing Data Centers

Autorzy: Andre Seuret, Arman Iranfar, Marina Zapater, John Thome, David Atienza
Opublikowane w: 2018 17th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Numer May 29 - June 1, 2018, 2018, Strona(/y) 587-595, ISBN 978-1-5386-1272-9
Wydawca: IEEE
DOI: 10.1109/itherm.2018.8419531

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

Autorzy: Artem Aleksandrovich Andreev, Fulya Kaplan, Marina Zapater, Ayse K. Coskun, David Atienza
Opublikowane w: 2018 IEEE International Symposium on Low Power Electronics and Design, Numer July 23 - 25, 2018, 2018, Strona(/y) 60-65, ISBN 978-1-4503-5704-3
Wydawca: Association for Computing Machinery
DOI: 10.1145/3218603.3218606

A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers

Autorzy: Arman Iranfar, Wellington Silva De Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza
Opublikowane w: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numer 6-9 October 2019, 2019, Strona(/y) 211-216, ISBN 978-1-7281-3915-9
Wydawca: IEEE
DOI: 10.1109/vlsi-soc.2019.8920309

Enhancing Two-Phase Cooling Efficiency through Thermal-Aware Workload Mapping for Power-Hungry Servers

Autorzy: Arman Iranfar, Ali Pahlevan, Marina Zapater, David Atienza
Opublikowane w: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numer March 25-29, 2019, 2019, Strona(/y) 66-71, ISBN 978-3-9819263-2-3
Wydawca: IEEE
DOI: 10.23919/date.2019.8715033

MAMUT: Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video Transcoding

Autorzy: Luis Costero, Arman Iranfar, Marina Zapater, Francisco D. Igual, Katzalin Olcoz, David Atienza
Opublikowane w: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numer March 25-29, 2019, 2019, Strona(/y) 558-563, ISBN 978-3-9819263-2-3
Wydawca: IEEE
DOI: 10.23919/date.2019.8715256

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

Autorzy: Marco Rios, William Simon, Alexandre Levisse, Marina Zapater, David Atienza
Opublikowane w: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numer October 6-9, 2019, 2019, Strona(/y) 34-39, ISBN 978-1-7281-3915-9
Wydawca: IEEE
DOI: 10.1109/vlsi-soc.2019.8920317

A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture

Autorzy: William Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza
Opublikowane w: Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19, Numer June 2-6, 2019, 2019, Strona(/y) 1-6, ISBN 9781-450367257
Wydawca: ACM Press
DOI: 10.1145/3316781.3317741

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Autorzy: Joao Vieira, Edouard Giacomin, Yasir Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
Opublikowane w: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numer October 6-9, 2019, 2019, Strona(/y) 160-165, ISBN 978-1-7281-3915-9
Wydawca: IEEE
DOI: 10.1109/vlsi-soc.2019.8920343

A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers

Autorzy: Wellington Silva de Souza, Arman Iranfar, Anderson Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza
Opublikowane w: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Numer October 6-9, 2019, 2019, Strona(/y) 230-231, ISBN 978-1-7281-3915-9
Wydawca: IEEE
DOI: 10.1109/vlsi-soc.2019.8920379

BLADE - A BitLine Accelerator for Devices on the Edge

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Opublikowane w: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19, Numer May 9-11, 2019, 2019, Strona(/y) 207-212, ISBN 9781-450362528
Wydawca: ACM Press
DOI: 10.1145/3299874.3317979

Gem5-X: A Gem5-based System Level Simulation Framework to Optimize Many-core Platforms

Autorzy: Yasir Qureshi, William Andrew Simon, Marina Zapater, David Atienza and Katzalin Olcoz
Opublikowane w: High Performance Computing (HPC 2019), Numer April 29 - May 2, 2019, 2019, Strona(/y) 20-31, ISBN 9781-510892545
Wydawca: Society for Modeling and Simulation International (SCS)
DOI: 10.22360/springsim.2019.hpc.008

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Autorzy: William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
Opublikowane w: 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020
Wydawca: IFIP/IEEE
DOI: 10.1109/vlsi-soc46417.2020.9344087

Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning

Autorzy: Arman Iranfar, Federico Terraneo, Gabor Csordas, Marina Zapater, William Fornaciari, David Atienza
Opublikowane w: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Strona(/y) 418-423, ISBN 978-3-9819263-4-7
Wydawca: IEEE
DOI: 10.23919/date48585.2020.9116510

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Autorzy: Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza
Opublikowane w: Proceedings of the 2020 on Great Lakes Symposium on VLSI, 2020, Strona(/y) 513-518, ISBN 9781450379441
Wydawca: ACM
DOI: 10.1145/3386263.3406923

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Autorzy: Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
Opublikowane w: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Numer 11733, 2019, Strona(/y) 34-47, ISBN 978-3-030-27561-7
Wydawca: Springer International Publishing
DOI: 10.1007/978-3-030-27562-4_3

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