Final Report Summary - TETTRA (Towards Enhanced III-V Tunnel Transistors)
The TETTRA project pursued two main objectives, the fabrication of n-type nanowire III-V tunnel FETs (field-effect transistors) and the characterization of interface and device properties. The first objective, the fabrication of n-type nanowire tunnel FETs is driven by the increasing demand for reducing the power consumption of logic devices. One route towards this goal is to utilize logic devices that with respect to the applied switching voltage are more voltage-sensitive than conventional silicon FETs. The voltage sensitivity is typically characterized by the inverse subthreshold slope describing the voltage change required to affect a current change of one order of magnitude. At higher voltage sensitivity the supply voltage that is necessary to switch the device can be reduced, which in turn reduces overall power consumption. One class of devices that potentially offers a higher voltage sensitivity are tunnel FETs, the functionality of which, however, critically depends on the choice of materials, the doping profile, and the interface properties.
The targeted realization for achieving high performance n-type tunnel FETs consists in a p-type GaSb segment as source, an intrinsic InGaAs segment as channel, and an n-type InAs segment as drain. The advantages of the InAs-GaSb system for tunnel FETs are multifold. First of all, the lattice constants of GaSb and InAs essentially match. This would allow for an interface void of misfit dislocations, which is relevant because misfit dislocations act as centers for trap-assisted tunneling. Secondly, the charge carrier concentrations of undoped InAs and GaSb are favorable for realizing a p-GaSb / n-InAs structure. Thirdly, the effective masses are small, which is beneficial for achieving high tunneling currents. Fourthly, effective masses do not differ too strongly, which is important as differences in the effective masses increase the electronic reflectance of the heterostructure interface reducing the tunneling current. Finally, the exact band alignment at the InAs/GaSb tunnel junction can by fine-tuned for instance by either adding small amounts of Ga to InAs or small amounts of Al to GaSb.
Within the framework of the TETTRA project we first investigated the fundamentals of the band-to-band tunneling process. Band-to-band tunneling is a more complex phenomenon as it may appear at first sight, because in contrast to conventional tunneling through a barrier, the nature of the charge carrier changes during band-to-band tunneling. In band-to-band tunneling charge carriers change from being electron-like to hole-like (or vice versa), which implies a change of sign and magnitude of the effective mass during tunneling. Using a k•p model the effect of this change of effective carrier mass was investigated. It turned out that the change of magnitude of the effective mass has a similar effect as a mismatch of the refractive index in optics, and that phenomena like total internal reflection can analogously occur in tunneling processes between materials having different effective carrier masses.
Like for most microelectronic devices of competitive dimensions, surface properties are crucially important for the performance of tunnel transistors. On the one hand, interface traps at the semiconductor gate-dielectric interface potentially lower the sensitivity of the device with respect to applied gate voltages and thereby diminish the main advantage of tunnel transistors compared to conventional FETs. On the other hand interface traps might contribute to trap assisted tunneling, which is also undesired. Efforts to characterize and optimize the interface properties were therefore one of the project objectives. The interface properties of III-V materials to high-k dielectric materials Al2O3 were investigated within the project, with focus on the effectiveness of surface passivating treatments like sulfur termination. It turned out that passivation of the semiconductor surface with sulfur prior to high-k deposition does have a pronounced effect on the interface trap density of Si as well as on the conductivity of InAs nanowires.
In order to allow for better understanding of the interface properties of nanowires, two novel measurement techniques for directly assessing interface charge densities of nanowire FETs were developed. The first is based on frequency-dependent analysis of the source-drain current-voltage characteristic of surround-gate FETs with the gate short-circuited to the drain. By comparing AC resistivity at low and high frequencies the interface charge density can be inferred.
The second is based on an independent characterization of charge carrier concentration and charge carrier mobility as a function of temperature and gate voltage. The Seebeck coefficient is employed to assess the charge carrier concentration within the nanowire, which, in combination with a resistance measurement delivers the charge carrier mobility (V. Schmidt et al. Appl. Phys. Lett. 104, 012113 (2014)). From the gate-voltage dependence of the charge carrier concentration (and knowing the geometry the FET), the interface trap level density can be obtained. This approach was successfully tested on InAs nanowires.
A main objective of the project, the fabrication of all III-V tunnel FETs and the characterization of the latter, could not be accomplished within the timeframe of the project, due to changes of and difficulties with the III-V nanowire transistor fabrication scheme. The time that was originally planned for tunnel FET device characterization was then used to develop and demonstrate a novel method for the thermoelectric characterization of nanowires (V. Schmidt et al. "Method for a complete, on-substrate, thermoelectric characterization of nanowires", to be submitted). Nevertheless, the efforts towards fabrication and characterization of GaSb-InAs tunnel transistors are ongoing and we are confident that the objective of fabricating an all III-V tunnel FET will be achieved in the near future.
The targeted realization for achieving high performance n-type tunnel FETs consists in a p-type GaSb segment as source, an intrinsic InGaAs segment as channel, and an n-type InAs segment as drain. The advantages of the InAs-GaSb system for tunnel FETs are multifold. First of all, the lattice constants of GaSb and InAs essentially match. This would allow for an interface void of misfit dislocations, which is relevant because misfit dislocations act as centers for trap-assisted tunneling. Secondly, the charge carrier concentrations of undoped InAs and GaSb are favorable for realizing a p-GaSb / n-InAs structure. Thirdly, the effective masses are small, which is beneficial for achieving high tunneling currents. Fourthly, effective masses do not differ too strongly, which is important as differences in the effective masses increase the electronic reflectance of the heterostructure interface reducing the tunneling current. Finally, the exact band alignment at the InAs/GaSb tunnel junction can by fine-tuned for instance by either adding small amounts of Ga to InAs or small amounts of Al to GaSb.
Within the framework of the TETTRA project we first investigated the fundamentals of the band-to-band tunneling process. Band-to-band tunneling is a more complex phenomenon as it may appear at first sight, because in contrast to conventional tunneling through a barrier, the nature of the charge carrier changes during band-to-band tunneling. In band-to-band tunneling charge carriers change from being electron-like to hole-like (or vice versa), which implies a change of sign and magnitude of the effective mass during tunneling. Using a k•p model the effect of this change of effective carrier mass was investigated. It turned out that the change of magnitude of the effective mass has a similar effect as a mismatch of the refractive index in optics, and that phenomena like total internal reflection can analogously occur in tunneling processes between materials having different effective carrier masses.
Like for most microelectronic devices of competitive dimensions, surface properties are crucially important for the performance of tunnel transistors. On the one hand, interface traps at the semiconductor gate-dielectric interface potentially lower the sensitivity of the device with respect to applied gate voltages and thereby diminish the main advantage of tunnel transistors compared to conventional FETs. On the other hand interface traps might contribute to trap assisted tunneling, which is also undesired. Efforts to characterize and optimize the interface properties were therefore one of the project objectives. The interface properties of III-V materials to high-k dielectric materials Al2O3 were investigated within the project, with focus on the effectiveness of surface passivating treatments like sulfur termination. It turned out that passivation of the semiconductor surface with sulfur prior to high-k deposition does have a pronounced effect on the interface trap density of Si as well as on the conductivity of InAs nanowires.
In order to allow for better understanding of the interface properties of nanowires, two novel measurement techniques for directly assessing interface charge densities of nanowire FETs were developed. The first is based on frequency-dependent analysis of the source-drain current-voltage characteristic of surround-gate FETs with the gate short-circuited to the drain. By comparing AC resistivity at low and high frequencies the interface charge density can be inferred.
The second is based on an independent characterization of charge carrier concentration and charge carrier mobility as a function of temperature and gate voltage. The Seebeck coefficient is employed to assess the charge carrier concentration within the nanowire, which, in combination with a resistance measurement delivers the charge carrier mobility (V. Schmidt et al. Appl. Phys. Lett. 104, 012113 (2014)). From the gate-voltage dependence of the charge carrier concentration (and knowing the geometry the FET), the interface trap level density can be obtained. This approach was successfully tested on InAs nanowires.
A main objective of the project, the fabrication of all III-V tunnel FETs and the characterization of the latter, could not be accomplished within the timeframe of the project, due to changes of and difficulties with the III-V nanowire transistor fabrication scheme. The time that was originally planned for tunnel FET device characterization was then used to develop and demonstrate a novel method for the thermoelectric characterization of nanowires (V. Schmidt et al. "Method for a complete, on-substrate, thermoelectric characterization of nanowires", to be submitted). Nevertheless, the efforts towards fabrication and characterization of GaSb-InAs tunnel transistors are ongoing and we are confident that the objective of fabricating an all III-V tunnel FET will be achieved in the near future.