European R&D marks milestones in steps to deliver fully European platform for space applications
The RISC-V instruction set architecture (ISA) leverages the power of open standard collaboration to enable freedom of innovation in computing design. This architecture has been implemented in a new synthesizable VHDL model of a processor called NOEL5. Released by Cobham Gaisler, NOEL5 complements the line of widely used radiation-tolerant LEON processors, enabling, amongst others, space missions. In its quest to create the first fully European hardware and software platform based on RISC-V ISA, the EU-funded project De-RISC has achieved its first milestones for space and aerospace designs. “The project is using Gaisler’s NOEL-V (LEON backwards) existing 64bit RISC-V processor in VHDL that shares many elements with the latest LEON5 core as the basis for the multicore design,” eeNews Europe reports. Summing up in part with regard to hardware, a De-RISC post on its first anniversary says “the project has developed the first version of the De-RISC MPSoC platform and the Performance Monitoring Unit, integrating observability (Cycle Contention Stack, Request Duration Counter) and controllability capabilities (Maximum-Contention Control Unit).” Cobham Gaisler is one of the four-member project consortium including also Barcelona Supercomputing Center and THALES, with Fent Innovative Software Solutions as coordinator.
Securing safety across components
These aren’t, however, its sole achievements to date. “The group has also ported the first prototype of the Fentis XtratuM XNG Hypervisor and LithOS ‘para-virtualised’ operating system to the NOEL-V processor.” Also known as a virtual machine monitor, the XtratuM Hypervisor is designed to meet safety-critical requirements and, in the context of De-RISC, will support creation of a combined hardware/software platform for future space and aeronautical applications developments in Europe. Regarding this software development, a news item on the ‘Design & Reuse’ marketplace notes that “validation activities which will generate evidence for commercialization have already started.” These will be assessed through implementation of the use cases for the platform’s time-critical and cybersecurity aspects as well as overall performance and data throughput.
Ground- and space-based market interest
The developments mark good progress in initial steps taken by De-RISC towards its goal to “guarantee access to made-in-Europe technology for aerospace applications through the use of RISC-V Instruction Set Architecture (ISA) in its final platform,” as noted in the project’s anniversary post. The project has since its commencement been included as a member of both the HIPEAC European network and RISC-V International global organisation. Developments have also attracted the attention of companies from the space market as well as the aerospace and automotive industries, with project partners continuing to present the potential of De-RISC at related events and conferences such as July’s Annual IEEE/IFIP International Conference on Dependable Systems and Networks. Consortium members held a virtual meeting at the end of October, closing the project’s first 12 months with presentations on their progress and various work package outcomes. During the online event, a demonstration was given of the first prototype of XtratuM XNG/SMP and LithOS running on the De-RISC platform. The focus of the De-RISC (De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer) project is to deliver critical and unique features with no United States export restriction and with multi-core interference migration, portability, fault-tolerance and open standards. The project comes to a close in March 2022. For more information, please see: De-RISC project website
Keywords
De-RISC, RISC-V, NOEL5, XtratuM Hypervisor, multicore design, multiprocessor system-on-a-chip, space applications