The NEXT project had among main objectives to provide a robust and reproducible 200mm integration route for sub-micron size magnetic elements in order to implement the AIC demonstrator.
This integration route has been developed to be CMOS compatible and thus uses standard equipments and technologies. The current available route is based on 0,35µm design rules and 3 metal levels. The magnetic elements (spin-valves, magnetic tunnel junction, magnetic multi-layers) can be patterned using either DUV or e-beam lithography. The range of addressable sizes can thus cover micron size to 50nm. This technological result can be applied to different magnetic applications such as memories, RF oscillators or Logic. To date, there is a very limited offer of 200mm magnetic processing; it is thus a real added value from the project.
This 200mm integration route is still at an R&D level as it is based on IBE patterning which cannot offer a sufficient uniformity to cope with memory industrial needs. However it is mature enough for advanced R&D and demonstration level. The main end-users of this result are thus European R&D centres or industrial R&D centre that cannot support the introduction of magnetic elements in the fabrication line. Although insufficient for memory application that demands highly uniform properties over the memory chip, this 200mm technology maybe interesting for non collective magnetic products (not based on large scale arrays) such as oscillators or Logic modules. In this case prototypes or limited production can be envisioned.