The main objective of this project was the development of cost-effective technologies for the manufacturing of photovoltaic (PV) cells based on thin (below 200micrometer) conventionally cast multicrystalline silicon wafers and EFG sheets. The EU's target cost for PV systems is 7Euro/Wp for the short and 3Euro/Wp for the medium term to help reach the White Paper target of 3GWp capacity by 2010.
To achieve the project's objective, a consortium was formed to develop innovative cell structures and fast (>1dm{2}/3sec) low-stress manufacturing technologies suitable for processing thin wafers with high yield.
Good progress has been achieved in all work packages of the project. All deliverables and milestones that were foreseen until the MTA meeting were fulfilled:
- Isotexturing processes have been developed and successfully demonstrated for both, multicrystalline wafers and EFG sheets. A wetbench that is suited for pre-diffusion cleaning and iso-texturing has been developed, designed and is currently under construction.
- P pastes resulting in two different target emitter sheet resistance values and P surface concentrations (A: 1019 P atoms/cm{3}; B: >1020 P atoms/cm{3}) when applied in the same optimised diffusion step have been developed and investigated. Samples of a boron paste have been supplied as well.
- Diffusion processes for homogeneous shallow emitter diffusion (60ohm/sq.) have been developed, applied and optimised.
- An advanced method for the parasitic edge removal applying no stress to the thin wafers has been developed based on a novel KOH paste suited for selective Si and PSG etching. Resulting fill factors of 76% and higher for POCl(3) diffused solar cells demonstrate clearly that the parasitic junction removal is successfully performed with this contactless method.
- Ag pastes allowing contacting shallow emitters (60ohm/sq.) have been developed, supplied to the project partners and successfully applied after optimising the contact firing step.
- Al pastes resulting in lower wafer bowing (? 1mm bow on ?125x125mm{2} wafers; full Al BSF) without degrading the Al back surface field (BSF) have been developed and successfully tested.
- A transverse probe double wavelength lifetime measurement set-up has been designed, built up and successfully tested. This set-up is in principle suited to extract and monitor the minority carrier lifetime in the wafer bulk and the surface recombination velocities of the rear and front surfaces and thus will help further process optimisation.
- Necessary improvement for handling and metallisation printing of thin wafers has been identified and specified.
Alternative rear side metallisation schemes applying local rear contacts, rear surfaces passivation and reflector layers and suited isolation processes are under development
First attempts to run advanced integrated process sequences that are suited for thin mc-Si and EFG wafers have been successfully executed.
Solar cell efficiencies in excess of 16.1 % have been achieved on thin mc-Si wafers (MTA milestone: > 15.5 %)
Solar cell efficiencies of 14.5% on 200 µm thin and > 15 % on 300 µm thick 100 cm2, 3 ohm cm EFG wafers have been demonstrated (MTA milestone on thin EFG: 14.5 %).
The advantageous results will be individually exploited by the respective project partners as described in the TIP (technology implementation plan):
- Merck and DuPont will try to commercialise the respective developed pastes. Astec will try to commercialise the developed wetbench concept.
- RWE SCHOTT Solar will try to implement the developed integral processing sequences including iso-texturing and shallow emitters.
- IMEC will disseminate the developed technologies through journal articles and conference proceedings and offer to transfer the gained know-how to interested PV companies.
- DIE-UNAP will offer the developed characterisation possibilities as commercially available service for a wider public and publish the scientifically relevant progress.
- Technion will publish the fundamental scientific know-how that has been gained and apply the etching and texturing technology also to other fields in the micro-electronic sector.