Risultati finali
Technical report and database of the secure IP supporting lattice cryptography (synthesizable in the FPGA-based IDV of WP5). Part 2.
IP for low-latency inter-node communication links, part 2Technical report and database (synthesizable in the FPGA-based IDV of WP5) of the IP for low-latency inter-node communication links. Part 2.
IP for fast task scheduling, part 2Technical report and database (synthesizable in the FPGA based IDV of WP5) of the IP for fast task scheduling. Part 2.
IP with data compression, part 1Technical report and database of the data compression IP (synthesizable in the FPGA-based IDV of WP5). Part 1.
AI Accelerator with mixed-precision including Posit, part 2Technical report and database of the data compression IP (synthesizable in the FPGA-based IDV of WP5). Part 2.
IP with data compression, part 2Technical report and database of the data compression IP (synthesizable in the FPGA-based IDV of WP5). Part 2.
AI Accelerator with mixed-precision including Posit, part 1Technical report and database of the AI accelerator IP (synthesizable in the FPGA-based IDV of WP5). Part 1.
IP for low-latency inter-node communication links, part 1Technical report and database (synthesizable in the FPGA-based IDV of WP5) of the IP for low-latency inter-node communication links. Part 1.
eXtreme Secure Crypto IP, part 1Technical report and database of the secure IP supporting lattice cryptography (synthesizable in the FPGA-based IDV of WP5). Part 1
IP for fast task scheduling, part 1Technical report and database (synthesizable in the FPGA based IDV of WP5) of the IP for fast task scheduling. Part 1.
The final report provides a summary of the dissemination actions undertaken during the project, as well as an overview of the plans of the partners to further disseminate the generated knowledge beyond the lifetime of the project.
Benchmarking design and planningBenchmark results carried out on the available HPC platforms.
Project Flyer & Dissemination MaterialsThe deliverable includes a set of communication and dissemination materials targeting a variety of stakeholders
Update of the collaboration plan with definition of common objectives and activities including milestonesUpdate on the report on the identification of common objectives and the definition and implementation of a collaboration plan, including the definition of the related project-specific milestones.
Evaluation planThis deliverable provides initial results of T6.4 to orchestrate evaluation of TEXTAROSSA solutions.
Final report of the collaboration plan with definition of common objectives and activities including milestonesFinal report on the identification of common objectives and the definition and implementation of a collaboration plan, including the definition of the related project-specific milestones.
Communication, Dissemination and Awareness Raising StrategyThis deliverable deals with the overall communication dissemination and raising awareness strategy of the project including target audience means to reach the audience and procedures to follow for this scope
Project management and handbookThe deliverable includes management processes and a complete handbook to share information set up internal processes and align activities
Collaboration plan with definition of common objectives and activities including milestonesThe final report provides a summary of the dissemination actions undertaken during the project as well as an overview of the plans of the partners to further disseminate the generated knowledge beyond the lifetime of the project
Requirements & SpecificationsDefinition of the specific technologies that will be used to exploit the applications.
Proof of Concept DesignDesign of HW and SW prototypes able to achieve the KPIs of the objectives.
Communication and Dissemination Report 1This deliverable reports on the dissemination actions undertaken during the first reporting period, as well as an overview of the plans of the partners to further disseminate the generated knowledge during the second period. It also includes the plan for the book. This report covers the training and networking too.
Consolidated specs of accelerators IPsTechnical report with consolidated specifications and requirements for the IPs that will be developed in WP2.
Gap analysisState-of-art of all technologies involved in the proposal
External Advisory Board reportsDescription of the advisory board and its actions to support technological TEXTAROSSA activities. It includes a “Lesson learnt'' section.
Initial application benchmarks and resultsThis deliverable provides intermediate results of T6.1-T6.3 tasks to present the initial benchmarks of applications and kernels i) adapted to heterogeneous architectures, ii) which exploit mixed-precision and iii) which benefit from dynamic runtime.
Data management planA data management plan will be discussed with all partners and will be implemented in agreement with Open Science directives
Final assessment and guidelinesThis deliverable summarizes adaptation of TEXTAROSSA features (T6.1-T6.3), provides guidelines, recommendations and final evaluation of the project (T6.4).
This deliverable consists on the final version of Vitis HLS flow, supporting the new HW defined in the project (selected FPGA family and board, mixed precision, inter-FPGA communication) at all the levels (emulation, simulation synthesis). The Vitis HLS flow version will be compliant with the interfaces defined toward the run-time.
Project Website & Social MediaThe deliverable includes website and social media (Facebook, Twitter) accounts managed by the project consortium.
Inter-FPGA Communication SW StackThis deliverable consists in the SW stack (kernel device driver and user-space library) needed to configure, control and monitor the Communication IP and to support its integration in the Vitis HLSflow.
Framework for efficient CNNs inference on a TEXTAROSSA nodeThis deliverable from T4.6 consists in the solutions to reduce communications for CNNs at the server level and a set of efficient CNN kernels for heterogeneous architectures enhanced with FPGA.
Efficient Memory Management strategies for CNNs at node levelThis deliverable consists of the SW layer implemented into the runtime system to manage CNN applications. This is an intermediate result of Task 4.6.
Mixed precision tool suiteThis deliverable from T4.3 consists of compilers, interfaces, libraries and tools needed to support mixed-precision computing in the node.
Task-based runtime systemsThis deliverable consists in OmpSs and StarPU adapted to TEXTAROSSA node and that support the features implemented in this WP. This is the outcome of tasks 4.2, 4.4 and 4.5.
The deliverable describes what actions will be undertaken to reduce project risks at all levels.
Pubblicazioni
Autori:
Giacomo Sansone, Marco Cococcioni
Pubblicato in:
International Conference on Applications in Electronics Pervading Industry, Environment and Society (ApplePies), 2022
Editore:
Springer Nature
DOI:
10.5281/zenodo.7134224
Autori:
Palazzari P., Iannone F.
Pubblicato in:
Special Numero of the International Journal of Parallel Programming, 2024
Editore:
Springer
Autori:
Galimberti, Andrea; Galli, Davide; Montanaro, Gabriele; Fornaciari, William; Zoni, Davide
Pubblicato in:
2022 25th Euromicro Conference on Digital System Design (DSD), Numero 1, 2022, ISBN 978-1-6654-7404-7
Editore:
IEEE
DOI:
10.1109/dsd57027.2022.00078
Autori:
Cattaneo, Daniele ; Magnani, Gabriele ; Cherubin, Stefano ; Agosta, Giovanni
Pubblicato in:
Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022), 2022, ISBN 978-3-95977-221-1
Editore:
Schloss Dagstuhl -- Leibniz-Zentrum fur Informatik
DOI:
10.4230/oasics.ng-res.2022.4
Autori:
Fornaciari W.; Agosta G.; Cattaneo D.; Denisov L.; Galimberti A.; Magnani G.; Zoni D.
Pubblicato in:
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numero 13, 2023, ISBN 979-8-3503-9624-9
Editore:
IEEE
DOI:
10.23919/date56975.2023.10137092
Autori:
Aldinucci M.; Agosta G.; Andreini A.; Ardagna C. A.; Bartolini A.; Cilardo A.; Cosenza B.; Danelutto M.; Esposito R.; Fornaciari W.; Giorgi R.; Lengani D.; Montella R.; Olivieri M.; Saponara S.; Simoni D.; Torquati M.
Pubblicato in:
Proceedings of the 18th ACM International Conference on Computing Frontiers, Numero 17, 2021
Editore:
ACM
DOI:
10.1145/3457388.3458508
Autori:
Marco Danelutto; Gabriele Mencagli; Alberto Ottimo; Francesco Iannone; Paolo Palazzari
Pubblicato in:
2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2023, Pagina/e 104-108
Editore:
IEEE press
DOI:
10.1109/pdp59025.2023.00023
Autori:
Giovanni Agosta; Daniele Cattaneo; William Fornaciari; Andrea Galimberti; Giuseppe Massari; Federico Reghenzani; Federico Terraneo; Davide Zoni; Carlo Brandolese; Massimo Celino; F. Iannone; Paolo Palazzari; Giuseppe Zummo; Massimo Bernaschi; Pasqua D'Ambra; Sergio Saponara; Marco Danelutto; Massimo Torquati; Marco Aldinucci; Yasir Arfat; Barbara Cantalupo; Iacopo Colonnelli; Roberto Esposito; Alb
Pubblicato in:
2021 24th Euromicro Conference on Digital System Design (DSD), 2021
Editore:
IEEE
DOI:
10.1109/dsd53832.2021.00051
Autori:
Galimberti, Andrea; Galli, Davide; Montanaro, Gabriele; Fornaciari, William; Zoni, Davide
Pubblicato in:
Proceedings of the 19th ACM International Conference on Computing Frontiers, Numero 5, 2022, Pagina/e 193-194
Editore:
acm
DOI:
10.1145/3528416.3530243
Autori:
Daniele Cattaneo, Alberto Maggioli, Gabriele Magnani, Lev Denisov, Shufan Yang, Giovanni Agosta, Stefano Cherubin
Pubblicato in:
Embedded Computer Systems: Architectures, Modeling, and Simulation: 23rd International Conference, SAMOS 2023, Numero 1, 2023, Pagina/e 469–477, ISBN 978-3-031-46076-0
Editore:
Springer
DOI:
10.1007/978-3-031-46077-7_33
Autori:
Marco Cococcioni; Federico Rossi; Emanuele Ruffaldi; Sergio Saponara
Pubblicato in:
Lecture Notes in Electrical Engineering, 2022, ISBN 978-3-030-95497-0
Editore:
Springer
DOI:
10.5281/zenodo.7128765
Autori:
Beaumont, Olivier; Collin, Jean-Alexandre; Eyraud-Dubois, Lionel; Vérité, Mathieu
Pubblicato in:
Proceedings of the 37th IEEE International Parallel & Distributed Processing Symposium, Numero 6, 2023, ISBN 979-8-3503-3766-2
Editore:
IEEE
DOI:
10.1109/ipdps54959.2023.00047
Autori:
Morais, Lucas; Jiménez-González, Daniel; Álvarez, Carlos
Pubblicato in:
9th BSC Doctoral Symposium, 2022
Editore:
BSC
Autori:
Hayfa Tayeb, Bérenger Bramas, Mathieu Faverge, Abdou Guermouche
Pubblicato in:
IEEE Heterogeneity in Computing Workshop (HCW’24), IPDPS 2024, 2024
Editore:
IEEE
Autori:
Montanaro G.; Galimberti A.; Colizzi E.; Zoni D.
Pubblicato in:
IEEE International Conference on Electronics, Circuits and Systems (ICECS), Numero 4, 2022, ISBN 978-1-6654-8823-5
Editore:
IEEE
DOI:
10.1109/icecs202256217.2022.9970992
Autori:
Andrea Galimberti; Gabriele Montanaro; William Fornaciari; Davide Zoni
Pubblicato in:
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023), Numero 6, 2023
Editore:
oasic
DOI:
10.4230/oasics.parma-ditam.2023.4
Autori:
Amirmasoud Ghiassi, Robert Birke and Lydia Y. Chen
Pubblicato in:
Cover Image Proceedings of the 2023 SIAM International Conference on Data Mining (SDM), Numero 2023, 2023, ISBN 978-1-61197-765-3
Editore:
SIAM
DOI:
10.1137/1.9781611977653.ch64
Autori:
F. Reghenzani; W. Fornaciari
Pubblicato in:
ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference, Numero 2, 2023
Editore:
ACM
DOI:
10.1145/3566097.3567851
Autori:
Filgueras Izquierdo, Antonio; Vidal, Miquel; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier
Pubblicato in:
2023 International Conference on Field Programmable Technology (ICFPT), Numero 1, 2024, Pagina/e 286-287, ISBN 979-8-3503-5911-4
Editore:
IEEE
DOI:
10.1109/icfpt59805.2023.00048
Autori:
Pasqua D'Ambra; Fabio Durastante; S M Ferdous; Salvatore Filippone; Mahantesh Halappanavar; Alex Pothen
Pubblicato in:
31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), Napoli, Marzo 2023, Numero 4, 2023, ISBN 979-8-3503-3763-1
Editore:
IEEE
DOI:
10.1109/pdp59025.2023.00017
Autori:
Piccoli, Michele; Zoni, Davide; Fornaciari, William; Massari, Giuseppe; Marco, Cococcioni; Federico, Rossi; Sergio, Saponara; Emanuele, Ruffaldi
Pubblicato in:
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023), Numero 2, 2023
Editore:
oasic
DOI:
10.4230/oasics.parma-ditam.2023.6
Autori:
Reghenzani, Federico; Zhishan, Guo; Luca, Santinelli; Fornaciari, William
Pubblicato in:
2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2022, Pagina/e 27-39, ISBN 978-1-6654-9998-9
Editore:
IEEE
DOI:
10.1109/rtas54340.2022.00011
Autori:
Albeerto Ottimo; Gabriele Mencagli; Marco Danelutto
Pubblicato in:
Proceedings - 2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2023, 2023, Pagina/e 92-99
Editore:
IEEE Press
DOI:
10.1109/pdp59025.2023.00021
Autori:
Filgueras Izquierdo, Antonio; Alvarez, Carlos; Jiménez González, Daniel
Pubblicato in:
9th BSC Doctoral Symposium, 2022
Editore:
BSC
Autori:
Tayeb, Hayfa; Bramas, Bérenger; Guermouche, Abdou; Faverge, Mathieu
Pubblicato in:
COMPAS 2022 – Conférence francophone d’informatique en Parallélisme, Architecture et Système, Numero 6, 2022
Editore:
INRIA
Autori:
William Fornaciari; Federico Terraneo; Giovanni Agosta; Zummo Giuseppe; Luca Saraceno; Giorgia Lancione; Daniele Gregori; Massimo Celino
Pubblicato in:
Lecture Notes in Computer Science ISBN: 9783031150739, Numero 7, 2022
Editore:
Springer
DOI:
10.1007/978-3-031-15074-6_27
Autori:
Marco Cococcioni; Federico Rossi; Emanuele Ruffaldi; Sergio Saponara
Pubblicato in:
Conference on Next Generation Arithmetic CoNGA, Numero 5, 2022, ISBN 9783031097782
Editore:
Springer
DOI:
10.1007/978-3-031-09779-9_8
Autori:
Galli, Davide; Galimberti, Andrea; Fornaciari, William; Zoni, Davide
Pubblicato in:
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2022), Numero 4, 2022, ISBN 9783031150739
Editore:
Springer
DOI:
10.1007/978-3-031-15074-6_20
Autori:
Antonio Filgueras; Miquel Vidal; Daniel Jiménez-González; Carlos Álvarez; Xavier Martorell
Pubblicato in:
2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, ISBN 979-8-3503-1205-8
Editore:
IEEE
DOI:
10.1109/fccm57271.2023.00041
Autori:
Pericle Perazzo, Stefano Di Matteo, Gianluca Dini, Sergio Saponara
Pubblicato in:
Computers and Electrical Engineering, Numero 118, 2024, ISSN 0045-7906
Editore:
Pergamon Press Ltd.
DOI:
10.1016/j.compeleceng.2024.109327
Autori:
M. Turisini, R. Ammendola, A. Biagioni, A. Ciardiello, P. Cretaro, O. Frezza, G. Lamanna, F. Lo Cicero, A. Lonardo, M. Martinelli, R. Piandani, D. Soldi, P. Vicini
Pubblicato in:
Journal of Instrumentation, Numero 17480221, 2022, ISSN 1748-0221
Editore:
Institute of Physics
DOI:
10.1088/1748-0221/17/04/c04002
Autori:
Davide Zoni; Andrea Galimberti; William Fornaciari
Pubblicato in:
ACM Comput. Surv., Numero 1, 2023, Pagina/e 1-33, ISSN 0360-0300
Editore:
Association for Computing Machinary, Inc.
DOI:
10.1145/3593044
Autori:
Marco Cococcioni; Federico Rossi; Emanuele Ruffaldi; Sergio Saponara
Pubblicato in:
IEEE Transactions on Emerging Topics in Computing, Numero 21686750, 2021, ISSN 2168-6750
Editore:
IEEE Computer Society
DOI:
10.1109/tetc.2021.3120538
Autori:
D. Zoni;A. Galimberti
Pubblicato in:
Journal of Systems Architecture, Numero 13837621, 2022, ISSN 1383-7621
Editore:
Elsevier BV
DOI:
10.1016/j.sysarc.2022.102476
Autori:
Pasqua D’Ambra, Fabio Durastante, Salvatore Filippone
Pubblicato in:
Software Impacts, Numero 15, 2023, ISSN 2665-9638
Editore:
Elsevier
DOI:
10.1016/j.simpa.2022.100463
Autori:
Giovanni Agosta, Marco Aldinucci, Carlos Alvarez, Roberto Ammendola, Yasir Arfat, Olivier Beaumont, Massimo Bernaschi, Andrea Biagioni, Tommaso Boccali, Berenger Bramas, Carlo Brandolese, Barbara Cantalupo, Mauro Carrozzo, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Iacopo Colonnelli, Paolo Cretaro, Pasqua D’Ambra, Marco Danelutto, Roberto Esposito, Lionel Eyraud-Dubois, Antonio Filg
Pubblicato in:
Microprocessors and Microsystems, Numero 01419331, 2022, ISSN 0141-9331
Editore:
Elsevier BV
DOI:
10.1016/j.micpro.2022.104679
Autori:
Lucas Morais; Carlos Álvarez; Daniel Jiménez-González; Juan Miguel de Haro; Guido Araujo; Michael Frank; Alfredo Goldman; Xavier Martorell
Pubblicato in:
IEEE Transactions on Computers, Numero 18, 2024, Pagina/e 138 - 151, ISSN 0018-9340
Editore:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/tc.2023.3323781
Autori:
Massimo Bernaschi; Alessandro Celestini; Flavio Vella; Pasqua D'Ambra
Pubblicato in:
IEEE transactions on parallel and distributed systems (Online) 34 (2023): 2365–2376. doi:10.1109/TPDS.2023.3287238, Numero 3, 2023, ISSN 1045-9219
Editore:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/tpds.2023.3287238
Autori:
Daniele Cattaneo, Michele Chiari, Giovanni Agosta, Stefano Cherubin
Pubblicato in:
SoftwareX, Numero 20, 2022, ISSN 2352-7110
Editore:
Elsevier BV
DOI:
10.1016/j.softx.2022.101238
È in corso la ricerca di dati su OpenAIRE...
Si è verificato un errore durante la ricerca dei dati su OpenAIRE
Nessun risultato disponibile