Periodic Reporting for period 2 - SpinAge (Weighted Spintronic-Nano-Oscillator-based Neuromorphic Computing System Assisted by laser for Cognitive Computing)
Reporting period: 2022-04-01 to 2023-03-31
SpinAge's goal is to design a high performance neuromorphic computing system benefiting from spintronics, electronics and photonics. This requires contribution from each partner in the consortium. The steps required to achieve this includes fabricating and analyzing spintronic components and integrates these elements homogeneously in the backend of a CMOS wafer. These types of spintronic devices are expected to reduce energy consumption and footprint compared to traditional technologies. These spintronic devices include spin torque nano oscillators (STNO), weighted spin hall nano oscillators(WSHNOs), and also magnetic memories as weights (to build a Weighted STNO: WSTNO). We need to build the CMOS analog front-end for the spintronic oscillators, controlling the neuromorphic network through CMOS and reading out the local temperature of the oscillators for controlling the output power of the laser. this is critical for proving that spintronic combined with CMOS can offer low-power systems for future AI hardware. TO cover a wide range of frequency, we use two types of oscillators at lower frequency range (INL) and very high frequency range (NANOSC). AU and CSIC are responsible to build the interfacing circuits for these oscillators. WSHNOs need memristors as close as possible to the SHNO which is also critical to gain the area efficiency of weighted neuron implementation using spintronic and memristor (POLIMI) devices. This will enable high-density, low-power neural networks for AI for both cloud and edge computing. Find proper materials for designing WSHNOs and WSTNOs require proper choose of material and precise characterization of such devices which is done through THz signals which is done by UG in SpinAge. One more critical component here is to have access to very energy-efficient low-power VCSELs for implementing the photonic layer for shining laser on the components in the spintronic layer which is done by TYN in SpinAge.
So far the following progresses have been made:
1. The proof-of-concept Weighted Spin Torque Nano-Oscillator was designed, fabricated and experimentally verified. A multifunctional MTJ stack was developed. Key performance indicators, such as TMR, yield and oscillation power were tracked and continuously improved on the wafer level.
2. During 1RP, the primary focus was on designing, fabricating, and optimizing primary and novel WSHNOs. In the second period, NanOsc primarily collaborated with other partners, mainly CSIS and POLIMI, to conduct the necessary SHNO characterization for CMOS interface design and pursue the idea of monolithic integration of SHNOs and memristors.
3. We designed STNO front end successfully fabricated and tested. In the second period, AU worked on device characterization (memristors, STNOs and SHNOs) as well as the effect of temperature on such devices together with other partners. Furthermore, AU has been working on the design and implementation of CMOS front-end for controlling the laser, reading out the temperature, and reading out the STNOs.
4. During 1RP, CSIC focused on the initial electrical model of the SHNO proposed by NANOSC, and searched for the best LNA architecture for the application. In 2RP, work has been done on improving the SHNO output impedance and noise models, together with NANOSC, and presenting a new single-to-differential LNA architecture. Finally, CSIC is starting with the design of the CMOS control circuitry of the gold standard 16x16 1T1R neural network SNN.
5. Memristor devices were optimized in combination with SHNOs in terms of forming voltage and current capability. The temperature dependence of the memristor characteristics was studied and compact models were developed for circuit simulations. Memristor arrays with sizes between 8x8 and 16x16 have been developed and the in-memory matrix-vector multiplication (MVM) operation was demonstrated experimentally.
6. During 1RP, the design and processing of VCSELs was the primary focus. The work carried out in the second reporting period was design focused, attempting to find integration solutions that would allow for optical heating to be achieved at a sub-micron scale. In this period on top of extensive simulations, Microles fabrication processes have been studied.
7.Our investigation into terahertz radiation in MTJ stacks revealed that the thickness of the layers hindered signal detection. Moreover, we employed the TRMOKE technique to precisely determine the loss and frequency of the STT-MTJs. We developed a novel experimental setup to investigate the impact of laser-induced heating on device performance. Meanwhile, we conducted THz measurements on various SHNO stacks fabricated by NANOSC and are currently analyzing the results.
1. The proof-of-concept Weighted Spin Torque Nano-Oscillator was designed, fabricated and experimentally verified. A multifunctional MTJ stack was developed. Key performance indicators, such as TMR, yield and oscillation power were tracked and continuously improved on the wafer level.
2. During 1RP, the primary focus was on designing, fabricating, and optimizing primary and novel WSHNOs. In the second period, NanOsc primarily collaborated with other partners, mainly CSIS and POLIMI, to conduct the necessary SHNO characterization for CMOS interface design and pursue the idea of monolithic integration of SHNOs and memristors.
3. We designed STNO front end successfully fabricated and tested. In the second period, AU worked on device characterization (memristors, STNOs and SHNOs) as well as the effect of temperature on such devices together with other partners. Furthermore, AU has been working on the design and implementation of CMOS front-end for controlling the laser, reading out the temperature, and reading out the STNOs.
4. During 1RP, CSIC focused on the initial electrical model of the SHNO proposed by NANOSC, and searched for the best LNA architecture for the application. In 2RP, work has been done on improving the SHNO output impedance and noise models, together with NANOSC, and presenting a new single-to-differential LNA architecture. Finally, CSIC is starting with the design of the CMOS control circuitry of the gold standard 16x16 1T1R neural network SNN.
5. Memristor devices were optimized in combination with SHNOs in terms of forming voltage and current capability. The temperature dependence of the memristor characteristics was studied and compact models were developed for circuit simulations. Memristor arrays with sizes between 8x8 and 16x16 have been developed and the in-memory matrix-vector multiplication (MVM) operation was demonstrated experimentally.
6. During 1RP, the design and processing of VCSELs was the primary focus. The work carried out in the second reporting period was design focused, attempting to find integration solutions that would allow for optical heating to be achieved at a sub-micron scale. In this period on top of extensive simulations, Microles fabrication processes have been studied.
7.Our investigation into terahertz radiation in MTJ stacks revealed that the thickness of the layers hindered signal detection. Moreover, we employed the TRMOKE technique to precisely determine the loss and frequency of the STT-MTJs. We developed a novel experimental setup to investigate the impact of laser-induced heating on device performance. Meanwhile, we conducted THz measurements on various SHNO stacks fabricated by NANOSC and are currently analyzing the results.
1. The integration of spintronic components with CMOS is an essential step to demonstrate the scalability of the proposed solution and the ability to build large neuromorphic networks. The discovery of novel non-volatile mechanisms to control the dynamic properties of spintronic devices will have the impact of energy efficiency and the range of applications.
2. Despite all the potentials described in the literature, SHNOs are still nascent nonlinear oscillators. Integrating them with non-volatile memories and utilizing them in a complex neural network with multiple layers is an innovative and unprecedented endeavor that NanOsc and other partners are pursuing.
3. Currently, there is not much work done on making full CMOS interfaces for spintronics devices, and also not any spice models for such devices. AU is developing full CMOS systems for interfacing STNOs (and WSTNOs) to be read in a low-power and compact mode.
4. So far there are no previous works implementing signal detection front-ends of SHNOs. In addition, the electrical models of these devices are not focused on the design of fully integrated RF circuits, so their improvement is fundamental for future designs. CSIC is centered on designing these front-ends, where their architecture is proposed to minimize area and power.
P5. The cointegration of memristors and SHNOs on the same chip is a fundamental breakthrough that paves the way for heterogeneous neural networks combining oxide-based memristors and magnetic materials/structures. This technological achievement will enable AI with higher performance and lower power consumption to support various applications.
6. Integrated VCSEL arrays open a path to the design and implementation of technologies combining photonic, magnetic and spintronic architectures. The combination of microlens arrays with VCSEL arrays enables precise interaction between optics and spintronics. Beyond this, there is much potential to exploit the interactions between light and magnet/spintronic devices.
7. Integrating lasers into optimized MTJ- and SHNO-based circuits can increase efficiency and reduce power consumption for various applications, including neuromorphic computing and general computation. This can lead to faster processing speeds and lower energy consumption, benefiting both the economy and society.
2. Despite all the potentials described in the literature, SHNOs are still nascent nonlinear oscillators. Integrating them with non-volatile memories and utilizing them in a complex neural network with multiple layers is an innovative and unprecedented endeavor that NanOsc and other partners are pursuing.
3. Currently, there is not much work done on making full CMOS interfaces for spintronics devices, and also not any spice models for such devices. AU is developing full CMOS systems for interfacing STNOs (and WSTNOs) to be read in a low-power and compact mode.
4. So far there are no previous works implementing signal detection front-ends of SHNOs. In addition, the electrical models of these devices are not focused on the design of fully integrated RF circuits, so their improvement is fundamental for future designs. CSIC is centered on designing these front-ends, where their architecture is proposed to minimize area and power.
P5. The cointegration of memristors and SHNOs on the same chip is a fundamental breakthrough that paves the way for heterogeneous neural networks combining oxide-based memristors and magnetic materials/structures. This technological achievement will enable AI with higher performance and lower power consumption to support various applications.
6. Integrated VCSEL arrays open a path to the design and implementation of technologies combining photonic, magnetic and spintronic architectures. The combination of microlens arrays with VCSEL arrays enables precise interaction between optics and spintronics. Beyond this, there is much potential to exploit the interactions between light and magnet/spintronic devices.
7. Integrating lasers into optimized MTJ- and SHNO-based circuits can increase efficiency and reduce power consumption for various applications, including neuromorphic computing and general computation. This can lead to faster processing speeds and lower energy consumption, benefiting both the economy and society.