De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer

Risultati finali

Analysis of the adherence of the RISCV platform to other critical realtime domains

Communication and Dissemination Plan and Report, First Update

Plan Update after one year and report on communication and dissemination activities.

Report analogous to D62 but for the period m13m24

Technical report summarizing the technical activities done until m12, and financial report including the financial statements of each partner and their use of the resources. Deviations w.r.t. plan will be justified, corrective actions taken, and risk management updates.

Final progress report

Report analogous to D62 but for the period m25m36

RISC-V XtratuM verification report

RISCV XtratuM hypervisor report describing the verification process and results

RISC-V SoC user manual, final update

Final update of the user manual for the RISCV SoC after design and verification

RISC-V SoC verification report, final update

Final update of the report describing the verification process and results for the RISCV SoC

RISC-V SoC user manual

User manual for the RISCV SoC after design and verification

Validation strategy definition

Description of the strategy for the validation of the different platform elements including the test plan and the assessment to perform with the use case

Final RISC-V platform prototype

Functional and validated platform including the RISCV SoC and XtratuM as well as required documentation for their use

RISC-V XtratuM verification report, final update

This deliverable will describe the verification process and results at the end of the development process including the support of the RISCV full virtualization extensions implemented in NOELV

Communication and Dissemination Plan

Initial communication and dissemination plan at project start.

RISC-V SoC verification report

Report describing the verification process and results for the RISCV SoC

Communication and Dissemination Plan and Report, Second Update

Plan Update after two years and report on communication and dissemination activities

Communication and Dissemination Report, Final Update

Final communication and dissemination report

Interim platform and domain requirement specification and definition

Interim aviation and space requirements for the platform, as well as requirements emanating from the platform itself.

Pubblicazioni

Open Source Hardware: An Opportunity For Critical Systems

Autori: Jimmy Le Rhun, Sylvain Girbal, Daniel Gracia Pérez
Pubblicato in: 2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), 2020
Editore: IEEE
DOI: 10.1109/dsn-w50199.2020.00019

De-RISC: Launching RISC-V into space

Autori: Jimmy Le Rhun, Vicente Nicolau, Antonio Garcia-Vilanova, Jan Andersson, Sergi Alcaide
Pubblicato in: OBDP2021 - 2nd European Workshop on On-Board Data Processing, 2021
Editore: ESA Conference ureau
DOI: 10.5281/zenodo.5575007

De-RISC: A Complete RISC-V Based Space-Grade Platform

Autori: Wessman, Nils-Johan; Malatesta, Fabio; Ribes, Stefano; Andersson, Jan; García Vilanova, Antonio; Masmano Tello, Miguel; Nicolau Gallego, Vicente; Gómez Molinero, Paco; Le Rhun, Jimmy; Alcaide Portet, Sergi; Cabo Pitarch, Guillem; Bas Jalón, Francisco; Benedicte Illescas, Pedro; Mazzocchetti, Fabio; Abella Ferrer, Jaume
Pubblicato in: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numero 1, 2022
Editore: IEEE
DOI: 10.23919/date54114.2022.9774557

De-RISC: the First RISC-V Space-Grade Platform for Safety-Critical Systems

Autori: Nils-Johan Wessman; Fabio Malatesta; Jan Andersson; Paco Gomez; Miguel Masmano; Vicente Nicolau; Jimmy Le Rhun; Guillem Cabo; Francisco Bas; Ruben Lorenzo; Oriol Sala; David Trilla; Jaume Abella
Pubblicato in: 2021 IEEE Space Computing Conference (SCC), 2021, ISBN 978-1-6654-2400-4
Editore: IEEE
DOI: 10.1109/scc49971.2021.00010

SafeSU: an Extended Statistics Unit for Multicore Timing Interference

Autori: Guillem Cabo; Francisco Bas; Ruben Lorenzo; David Trilla; Sergi Alcaide; Miquel Moreto; Carles Hernandez; Jaume Abella
Pubblicato in: 2021 IEEE European Test Symposium (ETS), 2021, ISBN 978-1-6654-1849-2
Editore: IEEE
DOI: 10.1109/ets50041.2021.9465444

De-RISC – Dependable Real-Time Infrastructurefor Safety-Critical Computer Systems

Autori: Gómez F., Masmano M., Nicolau V., Andersson J., Le Rhun J, Trilla D., Gallego F., Cabo G., Abella J.
Pubblicato in: Ada User Journal, Numero VOL. 41 No. 2. June, 2020., 2020, Pagina/e 107-112, ISSN 1381-6551
Editore: Ada Language UK Ltd.

Risultati finali

Pubblicazioni

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