Periodic Reporting for period 2 - ORIGENAL (Origami electronics for three dimensional integration of computational devices)
Période du rapport: 2020-10-01 au 2022-03-31
Increasing the integrated circuits complexity by lateral scaling, known as Moore’s law, has been the major driving force for the semiconductor industry. Now, after more than 4 decades, new solutions need to be explored to further increase the transistor count, as traditional downscaling strategies are reaching their fundamental limits. One of the most promising directions is to exploit the third dimension in chip architectures.
The ORIGENAL project develops a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices. The key idea is to use a thin-film-transistor (TFT) technology on thin foil substrate, and then fold the substrate to achieve a dense 3D packaging with completely new integration architectures, addressing both traditional logic and neuromorphic computing schemes
The project focuses on the development of:
1. A suitable thin-film-transistor technology on ultrathin-foil,
2. Tailored 3D interconnects and device architectures,
3. The technology for high precision folding.
ORIGENAL will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.
The ORIGENAL project develops a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices. The key idea is to use a thin-film-transistor (TFT) technology on thin foil substrate, and then fold the substrate to achieve a dense 3D packaging with completely new integration architectures, addressing both traditional logic and neuromorphic computing schemes
The project focuses on the development of:
1. A suitable thin-film-transistor technology on ultrathin-foil,
2. Tailored 3D interconnects and device architectures,
3. The technology for high precision folding.
ORIGENAL will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.
In the second reporting of the ORIGENAL project significant steps towards the realization of a suitable thin-film-transistor technology on foil were made.
The process for NMOS FETs based on MoS2 were significantly optimized, so that now a stable and state-of-the-art process is available. WSe2 was identified as suitable material for PMOS FETs and a first successfully run was finished were NMOS and PMOS FETs were successfully realized on one plastic substrate next to each others.
For the devices there are now suitable models available to implement them into functional circuits and different circuits have been simulated.
The first concept of a folding tool is available and significant progress on the via technology and via bonding was made, so that in the final reporting period the targeted demonstrator can be realized
The process for NMOS FETs based on MoS2 were significantly optimized, so that now a stable and state-of-the-art process is available. WSe2 was identified as suitable material for PMOS FETs and a first successfully run was finished were NMOS and PMOS FETs were successfully realized on one plastic substrate next to each others.
For the devices there are now suitable models available to implement them into functional circuits and different circuits have been simulated.
The first concept of a folding tool is available and significant progress on the via technology and via bonding was made, so that in the final reporting period the targeted demonstrator can be realized
The ORIGENAL project is targeting a breakthrough for integrated circuits and microelectronics by laying the scientific foundations for a novel and disruptive approach of 3D integration. Therefore this project will have direct impact on the forefront science and also industry in different areas, including thin-film-transistor technology, 2D materials, memory and logics electronics, chip architecture, manufacturing equipment, and material synthesis.
By the proposed 3D integration scheme a significantly higher device density per area is possible, which directly translates into reduced energy consumption and reduced cost per computing power or storage place. This technology has the potential to continuously extend the integration density for more than 30 years after the scaling of the lateral dimensions has reached fundamental limits and thus will have a disruptive impact on the future of the semiconductor industry. In addition, the 3D integration ultimately opens up the route for a novel 3D highly interconnected architecture concept required for reconfigurable electronics or neuromorphic computing.
By the proposed 3D integration scheme a significantly higher device density per area is possible, which directly translates into reduced energy consumption and reduced cost per computing power or storage place. This technology has the potential to continuously extend the integration density for more than 30 years after the scaling of the lateral dimensions has reached fundamental limits and thus will have a disruptive impact on the future of the semiconductor industry. In addition, the 3D integration ultimately opens up the route for a novel 3D highly interconnected architecture concept required for reconfigurable electronics or neuromorphic computing.