Periodic Reporting for period 5 - EPI SGA1 (SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI))
Reporting period: 2020-12-01 to 2021-12-31
The European Processor Initiative (EPI) is a project currently implemented under the first stage of the Framework Partnership Agreement (FPA: 800928), whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications. The first stage is the Special Grant Agreement of the European Processor Initiative (EPI-SGA1: 826647), which started in December 2018, aims to deliver a high-performance, low-power processor, implementing vector instructions and specific accelerators with high bandwidth memory access. The EPI processor, to be achieved within EPI-SGA1&2 will also meet high security and safety requirements. This will be achieved through intensive use of simulation, development of a complete software stack and tape-out in the most advanced semiconductor process node. SGA1 will provide a competitive chip that can effectively address the requirements of the HPC, AI, automotive and trusted IT infrastructure markets.
The EPI project is established as one of the cornerstones of this strategic plan – it gathers 28 partners from 10 European countries to develop the processor and ensure that the key competence of high-end chip design remains in Europe. European scientists and industry will be able to access exceptional levels of energy-efficient computing performance. Exascale systems will need to simultaneously meet challenges related to performance, system cost and energy-efficiency. SGA1 has used a holistic approach to refine the system architecture and its component specifications.
During the 3 years of EPI’s execution, SGA1 has worked towards fulfilling its objectives to a hybrid Exascale system developing:
- A novel, Exascale HPC-focused low-power processing system units (General Purpose Processor stream),
- An accelerator to increase energy efficiency for computing intensive tasks in HPC and AI (Accelerator stream),
- An automotive demonstration platform to test the relevance of the previous components in an automotive context paving the way for SGA2 (Automotive stream).
SGA1 has shared a strong set of common technology between these three different development streams. Starting with a co-design approach using a holistic strategy to match the application needs and the technical solutions implemented, defining the global architecture (hardware and software). A common design methodology has been established and a silicon process selected, 6nm for the General Purpose Processor and 22nm for the accelerator. Security is an essential topic and guidelines have been defined for all EPI products. A common and holistic approach for power management has been devised.
Starting from the selection of cutting-edge processor technology, a low-power design approach has been centered in the HW around massive parallelism, specialised architecture, low-voltage operating point and fine grain power management. The SW stack has been designed to integrate and take advantage of these features to achieve high-energy efficiency and maximise performance across a wide range of layers from the low level firmware, all the way up to system software and application run-times.
The EPI project is established as one of the cornerstones of this strategic plan – it gathers 28 partners from 10 European countries to develop the processor and ensure that the key competence of high-end chip design remains in Europe. European scientists and industry will be able to access exceptional levels of energy-efficient computing performance. Exascale systems will need to simultaneously meet challenges related to performance, system cost and energy-efficiency. SGA1 has used a holistic approach to refine the system architecture and its component specifications.
During the 3 years of EPI’s execution, SGA1 has worked towards fulfilling its objectives to a hybrid Exascale system developing:
- A novel, Exascale HPC-focused low-power processing system units (General Purpose Processor stream),
- An accelerator to increase energy efficiency for computing intensive tasks in HPC and AI (Accelerator stream),
- An automotive demonstration platform to test the relevance of the previous components in an automotive context paving the way for SGA2 (Automotive stream).
SGA1 has shared a strong set of common technology between these three different development streams. Starting with a co-design approach using a holistic strategy to match the application needs and the technical solutions implemented, defining the global architecture (hardware and software). A common design methodology has been established and a silicon process selected, 6nm for the General Purpose Processor and 22nm for the accelerator. Security is an essential topic and guidelines have been defined for all EPI products. A common and holistic approach for power management has been devised.
Starting from the selection of cutting-edge processor technology, a low-power design approach has been centered in the HW around massive parallelism, specialised architecture, low-voltage operating point and fine grain power management. The SW stack has been designed to integrate and take advantage of these features to achieve high-energy efficiency and maximise performance across a wide range of layers from the low level firmware, all the way up to system software and application run-times.
During the 37 months months of the project, from 1st of December 2018 to 31st of Dec 2021, EPI phase 1 (EPI SGA1- 826647) has reached its maturity phase, multiple technical challenges due to the core complexity of the technologies to be used and extra private budgets needed.
The EPI community mainly worked on a the following 4 goals : EPAC IP and test Chip showcasing EU accelerator, RHEA GPP showcasing EU CPU, EU technology based automotive demo and Co-design
o The EPAC RISC-V IPs were developed and proven on the first 1.0 release and it’s TapeOut as Test Chip in March 2021 .
Part of EPAC functionality have been successfully demonstrated. We have also developed the system software environment (Linux Kernel, LLVM vectorizing compiler, runtime libraries) to be able to run applications on the Test Chip and evaluate the performance. Emulation and simulation environments have been used for very early application developments and performance prediction.
The next iteration of the test chip will further improve the functionalities present while implementing fixes for the problems encountered in this version.
o RHEA General Purpose Processor is developed in secure and sovereign mode in SiPearl data center with SiPearl team and the help of multiple EPI partners, contributors in expertise or in IP’s. Due to slow ramp up in finance and human resources (despite 70 employees in SiPearl end of 2021), TapeOut has been pushed back to 2022, and will happen during the 1st half of SGA2.
o EU Automotive based on multiple EPI technologies, ARM Neoverse, RiscV5 accelerator, MPPA and eFPGA has been integrated to demonstrate its multiple use cases. (Demo Video has been produced)
o The codesign teams have selected a broad range of kernels and applications that have been ported to the ARM and RISC-V vector ISAs and used to dimension and co-design the GPP and EPAC architecture. In the GPP case the offered parameters to co-design focused mostly on memory architecture (cache size, address interleaving,...). In the RISC-V case it was also used in the design of the processor itself.
Global project execution with Microsoft project is integrating the multiple sub-projects components. Despite SiPearl delays in fund raising, all the external technologies needed in terms of EDA and core IP’s have been fully allocated during EPI-SGA1 to the EPI group.
Most of the legal milestones on terms of access to the IP’s have been sorted out with more than 100 engineers working in remote on the data center. This approach is also quite Covid-19 proof.
Despite delays at launch and complex legal proceeding, execution has been continued with a global worldwide visibility, EPI becoming, even in US, the gate keeper of HPC in EU.
The EPI community mainly worked on a the following 4 goals : EPAC IP and test Chip showcasing EU accelerator, RHEA GPP showcasing EU CPU, EU technology based automotive demo and Co-design
o The EPAC RISC-V IPs were developed and proven on the first 1.0 release and it’s TapeOut as Test Chip in March 2021 .
Part of EPAC functionality have been successfully demonstrated. We have also developed the system software environment (Linux Kernel, LLVM vectorizing compiler, runtime libraries) to be able to run applications on the Test Chip and evaluate the performance. Emulation and simulation environments have been used for very early application developments and performance prediction.
The next iteration of the test chip will further improve the functionalities present while implementing fixes for the problems encountered in this version.
o RHEA General Purpose Processor is developed in secure and sovereign mode in SiPearl data center with SiPearl team and the help of multiple EPI partners, contributors in expertise or in IP’s. Due to slow ramp up in finance and human resources (despite 70 employees in SiPearl end of 2021), TapeOut has been pushed back to 2022, and will happen during the 1st half of SGA2.
o EU Automotive based on multiple EPI technologies, ARM Neoverse, RiscV5 accelerator, MPPA and eFPGA has been integrated to demonstrate its multiple use cases. (Demo Video has been produced)
o The codesign teams have selected a broad range of kernels and applications that have been ported to the ARM and RISC-V vector ISAs and used to dimension and co-design the GPP and EPAC architecture. In the GPP case the offered parameters to co-design focused mostly on memory architecture (cache size, address interleaving,...). In the RISC-V case it was also used in the design of the processor itself.
Global project execution with Microsoft project is integrating the multiple sub-projects components. Despite SiPearl delays in fund raising, all the external technologies needed in terms of EDA and core IP’s have been fully allocated during EPI-SGA1 to the EPI group.
Most of the legal milestones on terms of access to the IP’s have been sorted out with more than 100 engineers working in remote on the data center. This approach is also quite Covid-19 proof.
Despite delays at launch and complex legal proceeding, execution has been continued with a global worldwide visibility, EPI becoming, even in US, the gate keeper of HPC in EU.
The design of a novel HPC processor family cannot be sustainable without thinking about possible additional markets that could support such long-term activities.
Thus, EPI has covered other areas such as the automotive sector, ensuring the overall economic viability of the initiative. EPI covers the complete range of expertise, skills and competencies needed to design and execute a sustainable roadmap for research and innovation in processor and computing technology fostering future exascale HPC and emerging applications, including Big Data, and automotive computing for autonomous vehicles. Development of a new processor to be at the core of future computing systems has been divided into 4 streams: Common Platform and global architecture stream, HPC general purpose processor stream, Accelerator stream and Automotive platform stream.
EPI-SGA2 will be natural extension of EPI-SGA1 and has already started on January,1st, 2022.
RHEA, GPP will be finished and proven, in EPI-SGA2, and RHEA2-Cronos started EPAC, test chip will be also finished and proven.
Other use cases for HPC will be explored.
Thus, EPI has covered other areas such as the automotive sector, ensuring the overall economic viability of the initiative. EPI covers the complete range of expertise, skills and competencies needed to design and execute a sustainable roadmap for research and innovation in processor and computing technology fostering future exascale HPC and emerging applications, including Big Data, and automotive computing for autonomous vehicles. Development of a new processor to be at the core of future computing systems has been divided into 4 streams: Common Platform and global architecture stream, HPC general purpose processor stream, Accelerator stream and Automotive platform stream.
EPI-SGA2 will be natural extension of EPI-SGA1 and has already started on January,1st, 2022.
RHEA, GPP will be finished and proven, in EPI-SGA2, and RHEA2-Cronos started EPAC, test chip will be also finished and proven.
Other use cases for HPC will be explored.