Periodic Reporting for period 3 - MASSTART (MASS manufacturing of TrAnsceiveRs for Terabit/s era)
Okres sprawozdawczy: 2022-01-01 do 2023-06-30
To address the next generation of transceivers in Data Centre (DC) infrastructures, targeting 800G and >1Tb/s aggregate data rates, expected to massively use Silicon Photonics based PICs, not only fabrication processes needs to be enhanced, but also the entire module manufacturing process, including packaging steps, and test and measurement operations. Indeed, with increasing manufacturing volumes, and increasing complexity level of the Silicon Photonics PICs, existing technologies are too limited in term of scalability, manufacturing throughput and test duration. As an example, today, assembling a ribbon fiber, held in a glass v-groove array, to a PIC through active alignment is typically limited by the assembly process time, an active final alignment.
MASSTART targets the exploitation of the following technologies to achieve the targets of enhanced performance at the lowest possible cost for the next generation 800Gb/s and higher Datacom transceivers :
* Glass waveguide technologies.
* Laser integration.
* Assembly techniques
* Characterization of the high speed modules
* Photonic/Electronic Integration, leveraging last decade development in the field of 3D packaging.
In addition to that, renowned end-users (module and network building blocks providers) are willing to lead developments, following a roadmap to On-Board module integration . Coordinating all these skills and know how, especially those related to assembly and test automation, at the European level within the MASSTART project, will allow Europe to unleash a breakthrough in Photonic transceivers assembly targeting data rates of at least to 400Gb/s aggregate bandwidth, in a relatively short term of 3-5 years. The mass automation in the assembly and the characterization is expected to bring down the cost for the rack-to-rack communication links to less than €1/Gb/s with minimum intervention by human hands. By addressing this major cost problem, MASSTART will reverse the current trend of job migration to Asia for exploitation of cheap labour and will render feasible the repatriation of many photonic jobs back to Europe.
The development of the MASSTART industrial and self-consistent process flow will be assessed by fabricating and characterizing demonstrators, addressing the mid-term requirements of next generation transceivers required by DC operators and covering both inter- and intra- DC applications. It will be devoted to help a standardization for future modules and their related packaging.
MASSTART targets the exploitation of the following technologies to achieve the targets of enhanced performance at the lowest possible cost for the next generation 800Gb/s and higher Datacom transceivers :
* Glass waveguide technologies.
* Laser integration.
* Assembly techniques
* Characterization of the high speed modules
* Photonic/Electronic Integration, leveraging last decade development in the field of 3D packaging.
In addition to that, renowned end-users (module and network building blocks providers) are willing to lead developments, following a roadmap to On-Board module integration . Coordinating all these skills and know how, especially those related to assembly and test automation, at the European level within the MASSTART project, will allow Europe to unleash a breakthrough in Photonic transceivers assembly targeting data rates of at least to 400Gb/s aggregate bandwidth, in a relatively short term of 3-5 years. The mass automation in the assembly and the characterization is expected to bring down the cost for the rack-to-rack communication links to less than €1/Gb/s with minimum intervention by human hands. By addressing this major cost problem, MASSTART will reverse the current trend of job migration to Asia for exploitation of cheap labour and will render feasible the repatriation of many photonic jobs back to Europe.
The development of the MASSTART industrial and self-consistent process flow will be assessed by fabricating and characterizing demonstrators, addressing the mid-term requirements of next generation transceivers required by DC operators and covering both inter- and intra- DC applications. It will be devoted to help a standardization for future modules and their related packaging.
The MASSTART project intends to establish a new assembly and test paradigm for next generation 800G and 1.6 T transceivers, including On-Board configuration, using robust, low cost, and high throughput packaging and test techniques, thus increasing Europe mass manufacturing capability for Datacom modules.
* PDKs have been developed by Bright Photonics, which include combination of multiple technologies (Si-Photonics, III-V, glass, assembly and packaging).
Complex routing and DRC issues addressed and solved by creating interconnects and routing for circuits connectivity with error-free implementation & DRC on connectivity and introduction of path tracing for circuit integrity.
New generation of assembly, coupling and packaging approaches faclitaed by creating packaging rules, packaging templates and importing fiducials, drivers, tias to the design and validation tool.
Tape-out of MASSTART inter- and intra- Data Center PICs using LETI and TEEM PDKs in Nazca realized.
* Advanced building block for Silicon Photonic fabrication habe been used LETI.
300mm Si-Photonics platform consist of passive device libraries as well as active ones (e.g. Ge photdiodes, Mach-Zehnder modulators).
Ultra low propagation losses achieved 1dB/cm.
* ALMAE developed III-V optical sources for high bit rate fiber transmission.
Developed components are emitting relatively high powers to compensate the losses.
The coupling losses are reduced by using innovative coupling techniques.
The develeped high performance Si-BH regrowth technology allows to achieve a) low capacitance for high modulation bandwidth, b) Spot size converter for high coupling efficiency , Spherical far field figure, c) Low consumption for efficient heating dissipation and low voltage operation.
Uncooled operation of 1.3-μm AlGaInAs strain-compensated MQW BH with more than 40mW facet power achieved.
* TEEM Photonics developed glass-based photonic circuits and assemblies.
ioNext offers a complete photonic platform with dedicated PDKs.
WAFT achieve high channel count uniformity, Insertion loss (incl. fiber-array) < 0.7dB.
Low profile solution demostrated for grating couplers.
A wafer-level PIC testing (edge-coupling) concept demonstrated using WAFT.
Evanescent coupling to SiN-on-Si waveguide layer achived for broadband and single-mode in O-band and C-band operation with losses < 1.5 dB from fiber to SiN.
*) Fraunhofer IZM developed 3D integration concept for next generation transceiver PICs.
The developed TSV technology is well aligned with Si-Photonics fabrication processes of LETI.
*) ficonTEC developed passive and active assembly concepts and dedicated machines for mass production.
*) Aristotle University of Thessaloniki developed automated testing platform Si-Ph DCIs.
Die tester allows to test rf and optical performances of the chips with automated tooling.
*) Tektronix introduced accelerating transceiver characterization and verification with machine learning features.
*) ADVA developed inter-DCI prototype testing platform.
*) NVIDIA Mellanox developed for intra-DCI prototypes PCB and testing platforms.
Results have been presented at
7th Symposium on OPTICAL INTERCONNECT IN DATA CENTERS at ECOC 2019 in Dublin
Exhibition ECOC 2019, Dublin
Photonics Days Berlin Brandenburg Conference 2020, MASSTART Session "Data Center Interconnects – Towards Mass Manufacturing"
Photonics Days Berlin Brandenburg Conference 2021, MASSTART Session "Data Center Interconnects"
Exhibition Photonics Days Berlin Brandenburg Conference 2021
Exhibition ECOC 2021, Bordeaux
* PDKs have been developed by Bright Photonics, which include combination of multiple technologies (Si-Photonics, III-V, glass, assembly and packaging).
Complex routing and DRC issues addressed and solved by creating interconnects and routing for circuits connectivity with error-free implementation & DRC on connectivity and introduction of path tracing for circuit integrity.
New generation of assembly, coupling and packaging approaches faclitaed by creating packaging rules, packaging templates and importing fiducials, drivers, tias to the design and validation tool.
Tape-out of MASSTART inter- and intra- Data Center PICs using LETI and TEEM PDKs in Nazca realized.
* Advanced building block for Silicon Photonic fabrication habe been used LETI.
300mm Si-Photonics platform consist of passive device libraries as well as active ones (e.g. Ge photdiodes, Mach-Zehnder modulators).
Ultra low propagation losses achieved 1dB/cm.
* ALMAE developed III-V optical sources for high bit rate fiber transmission.
Developed components are emitting relatively high powers to compensate the losses.
The coupling losses are reduced by using innovative coupling techniques.
The develeped high performance Si-BH regrowth technology allows to achieve a) low capacitance for high modulation bandwidth, b) Spot size converter for high coupling efficiency , Spherical far field figure, c) Low consumption for efficient heating dissipation and low voltage operation.
Uncooled operation of 1.3-μm AlGaInAs strain-compensated MQW BH with more than 40mW facet power achieved.
* TEEM Photonics developed glass-based photonic circuits and assemblies.
ioNext offers a complete photonic platform with dedicated PDKs.
WAFT achieve high channel count uniformity, Insertion loss (incl. fiber-array) < 0.7dB.
Low profile solution demostrated for grating couplers.
A wafer-level PIC testing (edge-coupling) concept demonstrated using WAFT.
Evanescent coupling to SiN-on-Si waveguide layer achived for broadband and single-mode in O-band and C-band operation with losses < 1.5 dB from fiber to SiN.
*) Fraunhofer IZM developed 3D integration concept for next generation transceiver PICs.
The developed TSV technology is well aligned with Si-Photonics fabrication processes of LETI.
*) ficonTEC developed passive and active assembly concepts and dedicated machines for mass production.
*) Aristotle University of Thessaloniki developed automated testing platform Si-Ph DCIs.
Die tester allows to test rf and optical performances of the chips with automated tooling.
*) Tektronix introduced accelerating transceiver characterization and verification with machine learning features.
*) ADVA developed inter-DCI prototype testing platform.
*) NVIDIA Mellanox developed for intra-DCI prototypes PCB and testing platforms.
Results have been presented at
7th Symposium on OPTICAL INTERCONNECT IN DATA CENTERS at ECOC 2019 in Dublin
Exhibition ECOC 2019, Dublin
Photonics Days Berlin Brandenburg Conference 2020, MASSTART Session "Data Center Interconnects – Towards Mass Manufacturing"
Photonics Days Berlin Brandenburg Conference 2021, MASSTART Session "Data Center Interconnects"
Exhibition Photonics Days Berlin Brandenburg Conference 2021
Exhibition ECOC 2021, Bordeaux
to standardize a set of glass waveguide based interfaces allowing high density PIC/fiber interconnects and laser/PIC coupling (loss<0.5dB pitch 15µm).
to develop a micro submount, with the related assembly process, to allow laser hybrid integration onto the PIC with alignment tolerances <1µm and angular error<0.5°.
to develop an optimized equipment and process for high throughput (improvement factor of 6) assembly of the aforementioned part together with the PIC.
to develop a full PIC fabrication process flow embedding TSVs (transmission loss lower than 2dB at 60GHz, pitch 40µm).
to setup test methodologies at wafer level for reduced time during characterization (improvement factor of 10 in characterisation in time) and yield analysis (targeted yield 90%).
to enhance the capabilities of flip chip bonders for enhanced performance and reduced assembly time by factor of 6.
to establish a standard process flow for Terabit/s class transceiver modules assembly and test.
to assess the full assembly & test flow by demonstrating two type of terabit class transceivers (C-Band 600Gb/s coherent for inter data center, and O-Band 1.6 Tb/s on-board for intra data center).
to manage a standardization activity for next generation Terabit/s transceivers, and the related packaging.
to develop a micro submount, with the related assembly process, to allow laser hybrid integration onto the PIC with alignment tolerances <1µm and angular error<0.5°.
to develop an optimized equipment and process for high throughput (improvement factor of 6) assembly of the aforementioned part together with the PIC.
to develop a full PIC fabrication process flow embedding TSVs (transmission loss lower than 2dB at 60GHz, pitch 40µm).
to setup test methodologies at wafer level for reduced time during characterization (improvement factor of 10 in characterisation in time) and yield analysis (targeted yield 90%).
to enhance the capabilities of flip chip bonders for enhanced performance and reduced assembly time by factor of 6.
to establish a standard process flow for Terabit/s class transceiver modules assembly and test.
to assess the full assembly & test flow by demonstrating two type of terabit class transceivers (C-Band 600Gb/s coherent for inter data center, and O-Band 1.6 Tb/s on-board for intra data center).
to manage a standardization activity for next generation Terabit/s transceivers, and the related packaging.