Periodic Reporting for period 2 - ICT-STREAMS (Silicon Photonics Transceiver and Routing technologies for High-End Multi-Socket Server Blades with Tb/s Throughput interconnect interfaces)
Berichtszeitraum: 2017-08-01 bis 2019-07-31
STREAMS aims to address the performance, cost and energy requirements for chip-to-chip, server-board and intra-rack level interconnections, allowing for almost linear reductions in physical space requirements and linear increases in throughput densities. STREAMS intends to develop a holistic mid-board transceiver and router device portfolio exploiting silicon photonic technologies and introducing Waelength Division Multiplexing (WDM) both as a capacity-enhancing as well as a low-energy routing mechanism. To achieve this, STREAMS aims to deliver a 1.6 Tb/s mid-board transceiver together with a 25.6 Tb/s-throughput mid-board routing engine onto the same electro-optic Polymer Circuit Board (PCB), releasing a point-to-point-linked 16-socket server board, increasing server-board density and throughput by >400% and 1600% respectively, at >90% reduced energy values.
The core objectives of ICT-STREAMS are:
1.Development of 50 Gb/s energy efficient photonics and electronics transceiver components.
2.Development of III-V on Si planar lasers and nano-amplifiers for WDM interconnection.
3.Development of a Thermal drift compensation subsystem (TDCS) employing non-invasive integrated monitors.
4.Development of a low-loss, low cost single-mode polymer Electro-optical PCB host platform and establishment of a cost-efficient electro-optic integration process.
5.Development of software controlled, energy efficient WDM Embedded Optic Modules with 1.6Tb/s throughput.
6.Development of a 25Tb/s throughput EOPCB-mounted, loss-less 16x16 WDM routing platform.
7.Establishment of Optical Path Interconnect (OPI) prototype: establishment and evaluation of ICT-STREAMS on-board optical chip-to-chip interconnection system for multi-socket server boards.
The core objectives of ICT-STREAMS are:
1.Development of 50 Gb/s energy efficient photonics and electronics transceiver components.
2.Development of III-V on Si planar lasers and nano-amplifiers for WDM interconnection.
3.Development of a Thermal drift compensation subsystem (TDCS) employing non-invasive integrated monitors.
4.Development of a low-loss, low cost single-mode polymer Electro-optical PCB host platform and establishment of a cost-efficient electro-optic integration process.
5.Development of software controlled, energy efficient WDM Embedded Optic Modules with 1.6Tb/s throughput.
6.Development of a 25Tb/s throughput EOPCB-mounted, loss-less 16x16 WDM routing platform.
7.Establishment of Optical Path Interconnect (OPI) prototype: establishment and evaluation of ICT-STREAMS on-board optical chip-to-chip interconnection system for multi-socket server boards.
STREAMS project has made significant progress during the last 2nd period and has achieved significant objectives with respect to its constituent technology blocks, system level architectures and its envisaged transceiver and routing demonstrators. Some small time-delays on the Si-photonic PIC fabrication and the board-level assemblies mainly due to the MPW run schedules have been successfully
absorbed with the project’s extension to 42 months that was decided after the first review meeting. Fabrication challenges have been experienced in the successful integration of III-V on SOI in-plane lasers and nanoamplifiers and thorough investigation as well as alternative solutions have been sought towards enabling a successful demonstration of the final system-scale interconnect architectures.
All constituent building blocks as well as the complete 8x-optical engine and the board-level routing system have been designed and evaluated, concluding to breakthrough results that are currently defining the state of the art in Si-based 400Gb/s and low-energy transceiver and routing systems for Datacom and computercom applications. More specifically, ICT-STREAMS demonstrated successfully: a) a 4-channel 200Gb/s transceiver sub-assembly comprising a Si-Pho 4-ch transceiver chip wirebonded to a 4-ch driver+TIA circuit and delivering energy consumption of only 4.2 pJ/bit, b) an 8-channel 400Gb/s Si-based transceiver, c) a record bandwidth-distance product transmission of 50Gb/sx52km using its electro-optical Si-based transmitter sub-assembly, d) on-board 8x8 and 16x16 AWGR elements assembled onto an EOPCB, and e) an ICT-STREAMS server blade interconnect for an 8x8 configuration via physical layer simulations, studying the interconnect architecture in two types of operation, namely: any-to-any and broadcasting. This has been based on a novel wavelength detuned transmission scheme for the transmitter interfaces that has been experimentally validated and takes into account the sub-optimal inband cross-talk of the AWGR, enabling in this way all-to-all p2p interconnection and highlighting the roadmap for fully-loaded AWGR-based transmission schemes even with suboptimal crosstalk values. Moreover, a variety of CLIPP devices to serve for the thermal drift compensation system of ICT-STREAMS have been designed and successfully evaluated in the first Silicon PIC active run (A1) so as to steer and hold the photonic stages to the optimal working point and compensate for the predicted severe crosstalk effects among the active components, included in the STREAMS demonstrators. A third run for EOCB (EOCB3) was been scheduled in order to host A2 and P3 silicon chips. The new EOCB3 boards were designed, fabricated and finally released in June 2019. During the last period, more than 55 papers have been accepted in scientific journals, magazines, international conferences and workshops. Finally, ICT-STREAMS consortium has participated in standardization bodies as well as in many events, workshops and exposition promoting the outcomes of the project. The consortium has been constantly monitoring the relevant IPR and the evolution in standards and the detailed exploitation outcomes and exploitation pathways per partner have been updated.
absorbed with the project’s extension to 42 months that was decided after the first review meeting. Fabrication challenges have been experienced in the successful integration of III-V on SOI in-plane lasers and nanoamplifiers and thorough investigation as well as alternative solutions have been sought towards enabling a successful demonstration of the final system-scale interconnect architectures.
All constituent building blocks as well as the complete 8x-optical engine and the board-level routing system have been designed and evaluated, concluding to breakthrough results that are currently defining the state of the art in Si-based 400Gb/s and low-energy transceiver and routing systems for Datacom and computercom applications. More specifically, ICT-STREAMS demonstrated successfully: a) a 4-channel 200Gb/s transceiver sub-assembly comprising a Si-Pho 4-ch transceiver chip wirebonded to a 4-ch driver+TIA circuit and delivering energy consumption of only 4.2 pJ/bit, b) an 8-channel 400Gb/s Si-based transceiver, c) a record bandwidth-distance product transmission of 50Gb/sx52km using its electro-optical Si-based transmitter sub-assembly, d) on-board 8x8 and 16x16 AWGR elements assembled onto an EOPCB, and e) an ICT-STREAMS server blade interconnect for an 8x8 configuration via physical layer simulations, studying the interconnect architecture in two types of operation, namely: any-to-any and broadcasting. This has been based on a novel wavelength detuned transmission scheme for the transmitter interfaces that has been experimentally validated and takes into account the sub-optimal inband cross-talk of the AWGR, enabling in this way all-to-all p2p interconnection and highlighting the roadmap for fully-loaded AWGR-based transmission schemes even with suboptimal crosstalk values. Moreover, a variety of CLIPP devices to serve for the thermal drift compensation system of ICT-STREAMS have been designed and successfully evaluated in the first Silicon PIC active run (A1) so as to steer and hold the photonic stages to the optimal working point and compensate for the predicted severe crosstalk effects among the active components, included in the STREAMS demonstrators. A third run for EOCB (EOCB3) was been scheduled in order to host A2 and P3 silicon chips. The new EOCB3 boards were designed, fabricated and finally released in June 2019. During the last period, more than 55 papers have been accepted in scientific journals, magazines, international conferences and workshops. Finally, ICT-STREAMS consortium has participated in standardization bodies as well as in many events, workshops and exposition promoting the outcomes of the project. The consortium has been constantly monitoring the relevant IPR and the evolution in standards and the detailed exploitation outcomes and exploitation pathways per partner have been updated.
ICT-STREAMS resolves current bandwidth and switch-latency barriers in multi-socket chip-to-chip configurations, allowing for 25Tb/s aggregate throughput, contention-free, on-the-fly massive data movements for multi-socket any-to-any interconnection, supporting in this way novel Rack Scale Architectures for compute, memory, and storage resource disaggregation concepts. Its optical engine will push the performance envelope of transceivers technology by means of number of WDM channels (32x) and channel data rate (50Gb/s) towards a 1.6Tb/s throughput optical engine with 3.75pJ/bit target power efficiency. Its single mode polymer Electro-Optical PCB employing adiabatic optical coupling concept with high-density, high-frequency RF and optical I/O interfaces intends to enable single step chip-to-board assembly, relaxing manufacturing time and cost requirements. STREAMS innovative Thermal Drift Compensation system is expected to bring significant impact on the real-life applicability of Si-Pho technology by monitoring and controlling the WDM Silicon Photonics components in a non-invasive way. In terms of integration, STREAMS will enable complete embedding of the gain structure in the back-end of the line (BEOL) process steps allowing for a fully CMOS compatible laser fabrication and the integrated in-plane lasers envisioned within the project will require no mechanical beam alignment to the Silicon chip.