MANGO: exploring Manycore Architectures for Next-GeneratiOn HPC systems

Risultati finali

In this deliverable a final report will be provided describing the final project validation, where all the applications will be run in the targeted real-time HPC system worked in the project.

Final (phase 3) Platform

In this deliverable we will provide the final platform developed according specification of WP1 and developments of WPs 2 and 3. The report will describe the advance of the platform through the three phases of building and manufacturing. We will also report the adaptation and fine tuning of the tile and manycore architectures when mapped on the final platform delivered in the project.

Phase 2 Platform

In this deliverable we will provide the phase 2 platform consisting on the new specific motherboards that will host the HN nodes. A detailed report showing the hw configuration will be provided. We will also provide servers and new power distribution system inside racks, interconnecting motherboards to the power source. A detailed report on the rack architecture will be provided.

Phase 1 Platform

In this deliverable we will provide the phase 1 platform consisting of the emulation boards for rapid architectural exploration within WPs 2 and 3. Details of the full hw configuration will be provided.

Report on the MANGO Architecture Specifications

A report will be delivered showing the specifications of the whole MANGO architecture, taking into account the initial applications requirements analysed in Task 1.1. This report will include the activities from Tasks 1.2, 1.3, and 1.4. Selected design flow tools will be also reported.

Progress Management Report - 1

These deliverables deal with the analysis of the activity of the consortium. As such it will evaluate pros and cons not only in terms of technical outcomes, but also in terms of organization, milestones, and end up with alternatives for steering next period directions.

Project Dissemination and Communication plan

This deliverable will include the plan regarding dissemination activities to be executed during the whole execution of the project, as conference participation, workshops planning, meetings with the Industrial Advisory Panel, coordination with other projects or forums, etc...

Programming Models and Compilers

This deliverable will produce a periodic report on the activities related to programming models (Task 2.1) and compiler support (Task 2.2).

Periodic dissemination report - 2

These two deliverables will include all the dissemination actions that have taken place during three different periods of time: for each reporting period of the project. These deliverables will be submitted to the commission after the meetings with the Advisory Panel and will collect its feedback.

Project Website

This deliverable will be design and implementation of a website as a major dissemination vehicle for the project, technology and product announcements.

Manycore Architectures

In this deliverable we will report on the manycore architectures researched in Task 3.2. A complete taxonomy and classification of architectures will be provided, highlighting the best configurations for the targeted applications and use cases of the project.

Report on MANGO Software Support

This deliverable will report the specifications of the Software stack and the protocol specifications for the MANGO architecture. Will include the activities from Tasks 1.5 and 1.6.

Progress Management Report - 2

These deliverables deal with the analysis of the activity of the consortium. As such it will evaluate pros and cons not only in terms of technical outcomes, but also in terms of organization, milestones, and end up with alternatives for steering next period directions.

Board and Rack Architectures

The report on Board Architectures will provide a detailed specification of the board (dedicated motherboard) including mechanical and electrical concept, selected key components, power and heat management concept, interface definitions, host software aspects as well as test and acceptance criteria. The report on Rack Architectures will provide a detailed specification of the power distribution within the rack. The specification will describe the power conversion stage from AC to 12V DC, including the battery part for power protection. It will also provide the electrical and mechanical characteristics of power connection devices and DC bus bars, and describe the heat management concept.

OS, Hypervisor Adaptation, and HPC Monitoring

This deliverable will produce a report that will describe the hierarchical control (including OS and hypervisor levels) developed to manage both the microfluidic cooling and energy recovery infrastructure in addition to the computing requirements. This report will also present the details of the SW architecture to fuel the user interface as well as the displays to be used in the platform.

Runtime Management Support

A report will be produced with the activities developed towards developing the Runtime Resource Manager for MANGO, located in Task 2.3. In particular this deliverable will produce a report detailing the implementation of the power- and thermal-aware strategies to control in a centralized manner the MANGO chip, board and rack. The main focus will be on the stability on the control and pro-active structure to advance possible thermal runaway situations that can degrade dramatically the performance of the overall MANGO HPC system.

Report on WP2 progress

This deliverable will report on working progress of WP2, in order to allow its proper monitoring at the review meeting in M18.

Final Implemented Real-Time HPC Software Support

In this deliverable we will report on the integrated software stack running on the MANGO platform. The deliverable will include an assessment of the performance of each component as well as of the entire stack.

Transcoding Applications

A report on transcoding applications adapted to the real-time HPC MANGO system will be provided. Will detail all the transformations and adaptations required for the efficient use of the system for the application.

Reporting of WP5 progress

This deliverable will report on working progress of WP5, in order to allow its proper monitoring at the review meeting in M18.

Final high-level workshop

This deliverable will give final presentation about project results and will conduct with new contacts and plans for further project collaborations.

Periodic dissemination report - 1

These twp deliverables will include all the dissemination actions that have taken place during three different periods of time: for each reporting period of the project. These deliverables will be submitted to the commission after the meetings with the Advisory Panel and will collect its feedback.

Tile Architectures

In this deliverable we will report the work performed in Task 3.1 where tile architectures will be deeply deployed, researched and analysed. The deliverable will consist on an exhaustive report on the different analysed tile organizations and a classification of the best configurations for the targeted applications and use cases of the project.

Report on Application Requirements

A report will be delivered showing the requirements from the target applications coming from Task 1.1. The report will include application scenarios from other domains related to HPC.

Pubblicazioni

The MANGO FET-HPC Project: An Overview

Autori: Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni
Pubblicato in: 2015 IEEE 18th International Conference on Computational Science and Engineering, 2015, Pagina/e 351-354, ISBN 978-1-4673-8297-7
Editore: IEEE
DOI: 10.1109/CSE.2015.57

Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation

Autori: Arman Iranfar, Ali Pahlevan, Marina Zapater, Martin Zagar, Mario Kovac, David Atienza
Pubblicato in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Pagina/e 949-954, ISBN 978-3-9819263-0-9
Editore: IEEE
DOI: 10.23919/date.2018.8342146

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

Autori: Artem Andreev, Fulya Kaplan, Marina Zapater, Ayse K. Coskun, David Atienza
Pubblicato in: Proceedings of the International Symposium on Low Power Electronics and Design - ISLPED '18, 2018, Pagina/e 1-6, ISBN 9781-450357043
Editore: ACM Press
DOI: 10.1145/3218603.3218606

Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?

Autori: Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza
Pubblicato in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Pagina/e 147-152, ISBN 978-3-9819263-0-9
Editore: IEEE
DOI: 10.23919/date.2018.8341994

Design of a Two-Phase Gravity-Driven Micro-Scale Thermosyphon Cooling System for High-Performance Computing Data Centers

Autori: Andre Seuret, Arman Iranfar, Marina Zapater, John Thome, David Atienza
Pubblicato in: 2018 17th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2018, Pagina/e 587-595, ISBN 978-1-5386-1272-9
Editore: IEEE
DOI: 10.1109/itherm.2018.8419531

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

Autori: Arman Iranfar, William Andrew Simon, Marina Zapater, David Atienza
Pubblicato in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Pagina/e 1-5, ISBN 978-1-5386-4881-0
Editore: IEEE
DOI: 10.1109/iscas.2018.8351785

Enhancing Two-Phase Cooling Efficiency through Thermal-Aware Workload Mapping for Power-Hungry Servers

Autori: 1. Iranfar, A. Pahlevan, M. Zapater, D. Atienza
Pubblicato in: 2019
Editore: IEEE

Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video Transcoding

Autori: 2. L. Costero, A. Iranfar, M. Zapater, F. Igual, K. Olcoz, D. Atienza
Pubblicato in: 2019
Editore: IEEE

Lightweight hardware support for selective coherence in heterogeneous manycore accelerators

Autori: A.Cilardo, M. Gagliardi, V. Scotti
Pubblicato in: 2019
Editore: IEEE

Enabling HPC for QoS-sensitive Applications: The MANGO Approach

Autori: José Flich, Giovanni Agosta, Philipp Ampletzerz, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinarić, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni
Pubblicato in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Pagina/e 702-707, ISBN 978-3-9815370-7-9
Editore: Research Publishing Services
DOI: 10.3850/9783981537079_1019

A Research Project on FPGA-accelerated Cryptographic Computing

Autori: Domenico Argenziano
Pubblicato in: 2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC), 2015, Pagina/e 574-577, ISBN 978-1-4673-9473-4
Editore: IEEE
DOI: 10.1109/3PGCIC.2015.187

"""A Configurable Shared Scratchpad Memory for GPU-like Processors"""

Autori: Alessandro Cilardo, Mirko Gagliardi, Ciro Donnarumma
Pubblicato in: Advances on P2P, Parallel, Grid, Cloud and Internet Computing, Volume 1 of the series Lecture Notes on Data Engineering and Communications Technologies, 2016, Pagina/e 3-14
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-49109-7_1

Implementation of an FFT Hardware Accelerator for Security Applications

Autori: Domenico Argenziano
Pubblicato in: 2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC), 2015, Pagina/e 256-259, ISBN 978-1-4673-9473-4
Editore: IEEE
DOI: 10.1109/3PGCIC.2015.188

"""Adaptive Modular Mapping to Reduce Shared Memory Bank Conflicts on GPUs"""

Autori: Innocenzo Mungiello, Francesco De Rosa
Pubblicato in: Advances on P2P, Parallel, Grid, Cloud and Internet Computing, Volume 1 of the series Lecture Notes on Data Engineering and Communications Technologies, 2016, Pagina/e 361-372
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-49109-7_34

Experimental Evaluation of Memory Optimizations on an Embedded GPU Platform

Autori: Innocenzo Mungiello
Pubblicato in: 2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC), 2015, Pagina/e 169-174, ISBN 978-1-4673-9473-4
Editore: IEEE
DOI: 10.1109/3PGCIC.2015.136

Securing the Cloud with Reconfigurable Computing: An FPGA Accelerator for Homomorphic Encryption

Autori: Alessandro Cilardo, Domenico Argenziano
Pubblicato in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Pagina/e 1622-1627, ISBN 978-3-9815370-7-9
Editore: Research Publishing Services
DOI: 10.3850/9783981537079_0745

TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip

Autori: Arman Iranfar, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, David Atienza
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numero 37/8, 2018, Pagina/e 1532-1545, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2017.2768417

Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers

Autori: Ali Pahlevan, Xiaoyu Qu, Marina Zapater, David Atienza
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numero 37/8, 2018, Pagina/e 1667-1680, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2017.2760517

Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers

Autori: Arman Iranfar, Marina Zapater, David Atienza
Pubblicato in: IEEE Transactions on Parallel and Distributed Systems, Numero 29/10, 2018, Pagina/e 2268-2281, ISSN 1045-9219
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2018.2827381

PowerTap: All-digital power meter modeling for run-time power monitoring

Autori: Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari
Pubblicato in: Microprocessors and Microsystems, Numero 63, 2018, Pagina/e 128-139, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2018.07.007

Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping

Autori: Edoardo Fusella, Alessandro Cilardo
Pubblicato in: ACM Journal on Emerging Technologies in Computing Systems, Numero 14/2, 2018, Pagina/e 1-11, ISSN 1550-4832
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3173463

Exploring manycore architectures for next-generation HPC systems through the MANGO approach

Autori: José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragić, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovač, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Koen Meinds, Hrvoje Mlinari
Pubblicato in: Microprocessors and Microsystems, Numero 61, 2018, Pagina/e 154-170, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2018.05.011

The Real-Time Linux Kernel

Autori: Federico Reghenzani, Giuseppe Massari, William Fornaciari
Pubblicato in: ACM Computing Surveys, Numero 52/1, 2019, Pagina/e 1-36, ISSN 0360-0300
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3297714

Big-Data Streaming Applications Scheduling Based on Staged Multi-armed Bandits

Autori: Karim Kanoun, Cem Tekin, David Atienza, Mihaela van der Schaar
Pubblicato in: IEEE Transactions on Computers, 2016, Pagina/e 1-1, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TC.2016.2550454

Diritti di proprietà intellettuale

ELECTRONIC DEVICE TO CONTROL TEMPERATURE AND COMPUTING PERFORMANCE OF AT LEAST ONE PROCESSING UNIT AND SYSTEM AND METHOD THEREOF

Numero candidatura/pubblicazione: EP 16722713
Data: 2016-02-15

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Pubblicazioni

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