Periodic Reporting for period 2 - EXTRA (Exploiting eXascale Technology with Reconfigurable Architectures)
Berichtszeitraum: 2017-03-01 bis 2018-08-31
In the EXTRA project, we prepare for the next generation High Performance Computing (HPC) nodes. If we want to obtain the maximal performance for the least amount of power, our consortium of companies and universities believes that such nodes will have to be heterogeneous, i.e. HPC systems will have to consist of different kinds of computing nodes depending on the applications to be implemented on them. This means that computation blocks should be tailored for specific tasks. However, instead of providing an entire range of different computation blocks for each task, we believe that computation blocks should be able to adapt themselves for specific tasks at specific moments in time. Such adaptable computation blocks are called reconfigurable architectures. If we can reconfigure these blocks while the system is working, the system is called run-time reconfigurable.
In the EXTRA project, we create a new and flexible exploration platform for developing such reconfigurable architectures and the tools to implement applications on them with run-time reconfiguration built-in from the start. The idea is to enable the joint optimization of architecture, tools, applications and reconfiguration technology in order to prepare for the necessary power-efficient HPC hardware nodes of the future.
As part of our project, we offer the European research community a research platform with open source architecture descriptions and tools for continued research on reconfiguration and for finding the next-generation system requirements. We want to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfiguration and reconfigurable computing.
In the EXTRA project, we create a new and flexible exploration platform for developing such reconfigurable architectures and the tools to implement applications on them with run-time reconfiguration built-in from the start. The idea is to enable the joint optimization of architecture, tools, applications and reconfiguration technology in order to prepare for the necessary power-efficient HPC hardware nodes of the future.
As part of our project, we offer the European research community a research platform with open source architecture descriptions and tools for continued research on reconfiguration and for finding the next-generation system requirements. We want to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfiguration and reconfigurable computing.
The EXTRA reconfigurable platform has been defined and studies have been performed on the analysis of the trade-offs in reconfiguration granularity, on the optimal off-loading to FPGA accelerators and on the system design exploration. Concurrently, we have developed Computer-Aided Design (CAD) tools to support the efficient use of the reconfigurable architecture platform. A tools frontend was designed within the CaaS (CAD-as-a-Service) concept and we have extended it with all the necessary tools to provide the entire design flow for reconfigurable systems. Our tools platform is called CAOS (CAD as an Adaptive OpenPlatform Service). The focus in the first project half has been on new research aspects needed for CAOS: polyhedral analysis and transformation, development of application analytical models and estimation of HW implementations, HW/SW Co-design for exascale reconfigurable computing, and integration and extension of vendor tools.
We have advertised our initial platform to the research community through a leaflet which was distributed at major conferences and exhibitions and through numerous presentations at workshops and conferences within the research domain. The goal is to convince other researchers to use our platform to enable research on tools for reconfigurable hardware design, on reconfigurable applications and on reconfigurable architectures. Of course, the EXTRA project partners also plan to use our platform to extend the state-of-the-art in reconfigurable HPC computing.
On the tools front, we have improved the configuration representation to enable just-in-time synthesis, we have analyzed the relations between synthesis, mapping, and placement and routing (P&R) tools as a first step to optimize the joint performance of these tools, and we have shown the advantages of using Virtual Coarse Grained Reconfigurable Arrays (VCGRAs) to provide a faster synthesis based on a hierarchical multi-level approach. We also started work on hardware monitoring and emergency management and the addition of hardware debugging tools to the framework.
On the applications front, we have focused on optimizations of the three EXTRA applications, on analyzing and detecting reconfiguration opportunities in these applications, and on the first implementations of reconfigurable functions and structures in reconfigurable devices.
Finally, on the reconfigurable architecture front, we have started to develop techniques and guidelines that improve the potential of reconfigurable technology, with a first focus on investigations of the optimal reconfiguration infrastructure, which will be integrated into the final project platform, on the development of tools that support on-chip configuration generation, and on the exploration of the interfaces between the heterogeneous parts of the final EXTRA platform.
We are currently finalizing the initial demonstrators, which will be shown on the project review.
We have advertised our initial platform to the research community through a leaflet which was distributed at major conferences and exhibitions and through numerous presentations at workshops and conferences within the research domain. The goal is to convince other researchers to use our platform to enable research on tools for reconfigurable hardware design, on reconfigurable applications and on reconfigurable architectures. Of course, the EXTRA project partners also plan to use our platform to extend the state-of-the-art in reconfigurable HPC computing.
On the tools front, we have improved the configuration representation to enable just-in-time synthesis, we have analyzed the relations between synthesis, mapping, and placement and routing (P&R) tools as a first step to optimize the joint performance of these tools, and we have shown the advantages of using Virtual Coarse Grained Reconfigurable Arrays (VCGRAs) to provide a faster synthesis based on a hierarchical multi-level approach. We also started work on hardware monitoring and emergency management and the addition of hardware debugging tools to the framework.
On the applications front, we have focused on optimizations of the three EXTRA applications, on analyzing and detecting reconfiguration opportunities in these applications, and on the first implementations of reconfigurable functions and structures in reconfigurable devices.
Finally, on the reconfigurable architecture front, we have started to develop techniques and guidelines that improve the potential of reconfigurable technology, with a first focus on investigations of the optimal reconfiguration infrastructure, which will be integrated into the final project platform, on the development of tools that support on-chip configuration generation, and on the exploration of the interfaces between the heterogeneous parts of the final EXTRA platform.
We are currently finalizing the initial demonstrators, which will be shown on the project review.
An open research platform on reconfigurable computing does not exist yet and its use in the research community opens up a wide range of possibilities for extending the state of the art in reconfigurable HPC computing.
We envisage that the EXTRA project will have both a direct and an indirect impact on future HPC markets. The direct impact relates to the activities for optimizing architectures and tools to design reconfigurable HPC systems (WP3, WP4, WP5 and WP7), as well as in the explicit exploitation of reconfigurability for three important applications in the HPC domain (WP6). The indirect impact will come from the opportunities arising from increased research efforts that will become possible with our architecture and tool exploration platform that is targeted at reconfigurable HPC systems.
The societal implications of the results of such research efforts are in more performant and especially more power-efficient computing in future HPC systems, opening up such systems for new applications that were impossible to compute before in a reasonable time and with a reasonable power budget.
We envisage that the EXTRA project will have both a direct and an indirect impact on future HPC markets. The direct impact relates to the activities for optimizing architectures and tools to design reconfigurable HPC systems (WP3, WP4, WP5 and WP7), as well as in the explicit exploitation of reconfigurability for three important applications in the HPC domain (WP6). The indirect impact will come from the opportunities arising from increased research efforts that will become possible with our architecture and tool exploration platform that is targeted at reconfigurable HPC systems.
The societal implications of the results of such research efforts are in more performant and especially more power-efficient computing in future HPC systems, opening up such systems for new applications that were impossible to compute before in a reasonable time and with a reasonable power budget.