Descripción del proyecto
FET Proactive: Minimising Energy Consumption of Computing to the Limit (MINECC)
TOLOP comprises investigations into three of the levels necessary for a paradigm shift in low-power electronics:1. Fabrication and measurement of devices which are inherently low-power in switching operation at room temperature2 . Theory of specific device implementations for each of those technologies to explain and validate the principles behind their low-power capabilities.3. Design of architecture to enable the circuit operation of these technologies for overall low-power circuit operation.There will be an investigation of the inherent losses at realistic switching rates, and estimations of the device-circuit-operation trade-offs for minimising energy consumption. Metrics such as the energy-delay product will be provided for each implementation and benchmarked against existing commercial and research technologies.The consortium brings together leading European institutions in this field, and allows the overall optimisation of energy consumption in realistic conditions, including device fabrication, device operation and circuit operation at several levels.Target outcomes:1. Novel single-atom, single-electron and spintronic devices will be investigated experimentally. In the first two cases, the structures are inherently CMOS-compatible whilst in the third a higher-risk approach will be taken whilst still addressing manufacturability2. Both non-Boolean implementations such as multi-valued logic and parallel logic, and optimised Boolean logic implementations will be addressed. Non Boolean logic has the potential for exponential improvement in power needs.3. Architectures and operating protocols will be designed to optimise the total power consumption of a circuit-level implementation, taking into account measured and estimated losses at realistic operating rates and temperatures
Device-level proof of concept will be achieved experimentally, driving the design of specific implementations, with theoretical investigation of viability in a realistic circuit
Tema(s)
Convocatoria de propuestas
FP7-ICT-2011-8
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Régimen de financiación
CP - Collaborative project (generic)Coordinador
SL2 4HD Stoke Poges
Reino Unido