Broadband over Powerlines that works and meets the standards and users expectations

Informations projet

POWERNET

N° de convention de subvention: 027953

Projet clôturé

Date de début 1 Novembre 2005

Date de fin 31 Mars 2008

Financé au titre de

• Information Society Technologies: thematic priority under the specific programme "Integrating and strengthening the European research area" (2002-2006).

Coût total € 2 319 375,00

Contribution de l’UE € 1 198 800,00

Coordonné par

TELSCOM A.G.
Switzerland

Résultats exploitables

Cognitive Broadband over Power Lines

The main project objective of the Powernet project is to develop and validate Cognitive Broadband over Power Lines (CBPL) Demonstration Units that meet the regulatory requirements concerning electro-magnetic (EM) radiation and can deliver high data rates while using with low transmit PSD and working at low signal to noise ratio. Powernet began with a small set of partners with the specific expertise suited to realise the Cognitive BPL (CBPL) system, as described in the Description of work. The project consortium has only 5 partners out of which 3 are SMEs, one research institute and one public electric utility company. The project had an ambitious objective of design and development CBPL system within in one year for first level of field trials (with off-the-shelf components) so as to confirm the design validation and to develop ASIC for the analog front end, which is one of the complex part of the planned CBPL system. The digital circuits were realized by FPGA, which can be later developed as a digital ASIC to complement analog ASIC for commercial exploitation. Based on the first set of trials the analog ASIC was developed in the second year, which was available at the end of second year. This chip was tested for its performance and was sent to WP2 to integrate with digital circuit boards and to develop new CBPL demonstrator units with error correction algorithms incorporated. During the phase 2, WP2 activities designed new interfaces with partitioned HW and SW between Analog board with new ASIC and digital circuits with the improved forward error correction algorithm (Reed-Solomon code) and cognitive algorithm. In the final phase of the project the focus was the integration of the analog ASIC into the CBPL Demonstrator Units and the second field trials using them. The AFE board was redesigned, the DSP board modified to receive a second ADC and the software adapted accordingly. Following successful integration tests in the laboratory, second set of trials were done during the extended period (Dec.2007 -Mar 2008). The CBPL Demonstrator Units were evaluated in the field and compared with PLC modems on the market, following the recommendations from the reviewers to benchmark the results. The performance investigations included measured data rate, BER, and EM radiation when the CBPL Demonstrator Units were in operation using different transmit PSD and channel bandwidths. The analysis of measurements leads to expected results: the CBPL Demonstrator Units performed better than the PLC modems on the market while using lower transmit PSD and lower EM radiation. Dissemination activities continued with number of presentations during the concertation meetings, and conferences, where it received a good response. The main target of dissemination was however the IEEE P1901 standardization activities. Powernet project continued to take an active part in IEEE 1901 standards and have their contribution integrated to Homeplug/Panasonic proposal which has been retained. The project also received number of enquiries for possible field trials on their electricity distribution networks. A number of contacts were also made for exploitation opportunities. These enquiries will be followed up after the completion of the project.