Periodic Reporting for period 3 - SEPHY (SPACE ETHERNET PHYSICAL LAYER TRANSCEIVER)
Okres sprawozdawczy: 2017-05-01 do 2018-12-31
The growing complexity of space systems is creating the need for high speed networking technologies to interconnect the different elements of a spacecraft. This interest has spurred initiatives by both ESA and NASA to define the next generation networking technologies for Space. In both cases, Ethernet has been the preferred choice due to its wide adoption in terrestrial applications and because it is fully specified in standards to ensure interoperability.
The main objective of this project is the development of a radiation hardened 10/100Mbps Ethernet physical layer transceiver for the space market that could enable Ethernet based on technologies to become an international space standard in future applications. An additional objective is to study the feasibility of a Gigabit Ethernet physical layer transceiver for space as the natural evolution of the 10/100 one and also to make sure the future IEEE 802.3 standards over a single twisted pair take into consideration the space sector requirements.
Finally, an engineering module of an Ethernet 10/100 PHY transceiver has been developed succesfully and, given the high maturity of the outcome of SEPHY, the partners will concentrate their efforts in finding ways for financing the qualification campaign so that the parts can be made available to the Space Community.
For furher information, please contact:
Ferrán Tejada CEO
ARQUIMEA INGENIERIA S.L.U.
C/Margarita Salas, 10
28919, Leganés, Madrid, SPAIN
Tel: +34 91 689 80 94
Fax: +34 91 182 15 77
E-mail: info@arquimea.com
The main objective of this project is the development of a radiation hardened 10/100Mbps Ethernet physical layer transceiver for the space market that could enable Ethernet based on technologies to become an international space standard in future applications. An additional objective is to study the feasibility of a Gigabit Ethernet physical layer transceiver for space as the natural evolution of the 10/100 one and also to make sure the future IEEE 802.3 standards over a single twisted pair take into consideration the space sector requirements.
Finally, an engineering module of an Ethernet 10/100 PHY transceiver has been developed succesfully and, given the high maturity of the outcome of SEPHY, the partners will concentrate their efforts in finding ways for financing the qualification campaign so that the parts can be made available to the Space Community.
For furher information, please contact:
Ferrán Tejada CEO
ARQUIMEA INGENIERIA S.L.U.
C/Margarita Salas, 10
28919, Leganés, Madrid, SPAIN
Tel: +34 91 689 80 94
Fax: +34 91 182 15 77
E-mail: info@arquimea.com
First year period summary
During this period, the basis of the project were set up with the description of the requirements and architecture of the future PHY. The design of the first test chip was developed. The goal of this phase was to prototype the most critical blocks of the Ethernet Transceiver, especially for 10BASET, which was achieved. However, the available Multi Project Wafer fabrication windows had a slight modification w.r.t the ones originally conceived in the proposal and so the phase 1 tape-out suffered a slight delay which implied that the overall project planning suffered a small deviation.
Second year period summary
The main goals in the second year were, on one hand to manufacture and test the test chip 1 (also known as TC1) and, on the other hand to reach a high level of maturity on the final device so that the target manufacturing goal of SEPHY could be achieved.
With respect to the first goal, the TC1 was successfully manufactured, assembled and preliminary tested for continuity and consumption with results in line with the expectations. In addition to that, a versatile and complex test setup was developed to allow testing the TC1 in standalone mode (to validate the TC1 blocks) and also in system mode in combination with an external FPGA where the digital code that will be included on SEPHY final chip could be preliminary validated.
Regarding the second goal, a huge effort were put in the design and simulation tasks in order to get a mature chip.
Final period summary
In the frame of the project an engineering module of an Ethernet 10/100 PHY transceiver was developed. It has been proved to be fully functional up to 20m in both 10BASET and 100BASE-TX modes with a very good radiation performance. The radiation testing of chip also showed very good performance. In terms of TID, the validation proved that the functionality of the parts is not affected at all up to the maximum dose tested (111 krad). With respect to the SEE radiation tests performed, the parts showed to be insensitive to latch-up up to the maximum energy used (62 MeVcm2/mg). In addition to that, the parts were sensitive to SEU/SET but with a very competitive BER and with a predicted SEU rate (GEO) considered to be low for standard GEO space programs. The network level tests were also satisfactory. The final SEPHY device was placed on a dedicated TTEthernet Equipment were a detailed suite of test cases, including Rate Constrained, Regular and Time Triggered Ethernet traffic, was successfully passed.
The EM developed will require minor upgrades before qualification basically to update configuration registers and ease the startup procedure, but in any case, they can be tested by interested parties upon request.
In term of the exploitation and commercialization, considering the SEPHY condition of radiation-hardened device, the proposed PHY transceiver mainly targets applications in the space sector. Nevertheless, the deterministic Ethernet protocol is quickly expanding to critical applications in other sectors, such as aviation, railway or nuclear.
The main results of the device are:
- Integrated high performance 100 Mb/s clock recovery circuitry requiring no external filters up to 20m.
- Full Duplex support for 10 and 100 Mb/s.
- Programmable loopback modes for easy system diagnostics.
- 3.3V/1.8V power supply.
- Extended temperature range from -55°C to 125°C.
- MII/RMII MAC communication interface.
- MI interface for MAC management and diagnostics.
- 15 years lifetime at maximum operating conditions.
- TID hardness greater than 100krad.
- SEU threshold LET>30MeV· cm²/mg.
- SEU Error Rate lower than 10e-10 errors/bit-day (@ <62 MeV· cm²/mg).
- SEL Threshold LET greater than 62 MeV· cm²/mg.
During this period, the basis of the project were set up with the description of the requirements and architecture of the future PHY. The design of the first test chip was developed. The goal of this phase was to prototype the most critical blocks of the Ethernet Transceiver, especially for 10BASET, which was achieved. However, the available Multi Project Wafer fabrication windows had a slight modification w.r.t the ones originally conceived in the proposal and so the phase 1 tape-out suffered a slight delay which implied that the overall project planning suffered a small deviation.
Second year period summary
The main goals in the second year were, on one hand to manufacture and test the test chip 1 (also known as TC1) and, on the other hand to reach a high level of maturity on the final device so that the target manufacturing goal of SEPHY could be achieved.
With respect to the first goal, the TC1 was successfully manufactured, assembled and preliminary tested for continuity and consumption with results in line with the expectations. In addition to that, a versatile and complex test setup was developed to allow testing the TC1 in standalone mode (to validate the TC1 blocks) and also in system mode in combination with an external FPGA where the digital code that will be included on SEPHY final chip could be preliminary validated.
Regarding the second goal, a huge effort were put in the design and simulation tasks in order to get a mature chip.
Final period summary
In the frame of the project an engineering module of an Ethernet 10/100 PHY transceiver was developed. It has been proved to be fully functional up to 20m in both 10BASET and 100BASE-TX modes with a very good radiation performance. The radiation testing of chip also showed very good performance. In terms of TID, the validation proved that the functionality of the parts is not affected at all up to the maximum dose tested (111 krad). With respect to the SEE radiation tests performed, the parts showed to be insensitive to latch-up up to the maximum energy used (62 MeVcm2/mg). In addition to that, the parts were sensitive to SEU/SET but with a very competitive BER and with a predicted SEU rate (GEO) considered to be low for standard GEO space programs. The network level tests were also satisfactory. The final SEPHY device was placed on a dedicated TTEthernet Equipment were a detailed suite of test cases, including Rate Constrained, Regular and Time Triggered Ethernet traffic, was successfully passed.
The EM developed will require minor upgrades before qualification basically to update configuration registers and ease the startup procedure, but in any case, they can be tested by interested parties upon request.
In term of the exploitation and commercialization, considering the SEPHY condition of radiation-hardened device, the proposed PHY transceiver mainly targets applications in the space sector. Nevertheless, the deterministic Ethernet protocol is quickly expanding to critical applications in other sectors, such as aviation, railway or nuclear.
The main results of the device are:
- Integrated high performance 100 Mb/s clock recovery circuitry requiring no external filters up to 20m.
- Full Duplex support for 10 and 100 Mb/s.
- Programmable loopback modes for easy system diagnostics.
- 3.3V/1.8V power supply.
- Extended temperature range from -55°C to 125°C.
- MII/RMII MAC communication interface.
- MI interface for MAC management and diagnostics.
- 15 years lifetime at maximum operating conditions.
- TID hardness greater than 100krad.
- SEU threshold LET>30MeV· cm²/mg.
- SEU Error Rate lower than 10e-10 errors/bit-day (@ <62 MeV· cm²/mg).
- SEL Threshold LET greater than 62 MeV· cm²/mg.
The ambition of the SEPHY project is to put Europe at the forefront of the adoption of Ethernet PHYs in space systems. This goal is ambitious as 1) the Ethernet commercial and industrial IC market is dominated by non-European companies (Intel, Broadcom, Marvell, LSI, etc. and 2) Ethernet PHYs are complex mixed signal devices and there are no Ethernet PHYs qualified for space. Since the PHYs are a key component in Ethernet, the success of SEPHY would not only ensure non dependence but possibly also leadership position over other countries. Therefore the goals are ambitious both technically and in terms of the long term strategic impact of the project.
The SEPHY project also has the ambition to reuse the developed PHYs for other mission critical applications. Those include automotive, avionics and industrial systems in which Ethernet is already or is likely to be the dominant networking technology. This extends the ambition of the proposal beyond space systems.
The project also includes forward looking activities to enable the future development of a Gigabit Ethernet PHY for space. This work is highly innovative and involves the use of advanced signal processing, communications and electronics (analogue and digital). Also within those studies, different standarts have been analized, such as 1000BASE-T1 or 1000BASE-CX, which will be suitable for space applications.
Additionally, a study and implementation of advanced mitigation techniques for single events effects has been done. In particular, the research of UAN on fault tolerant signal processing implementations was used to optimize the protection of the PHYs. Additionally IHP has also investigated novel mitigation techniques at architectural level to improve the overall digital implementation reliability. Finally, UAN has also investigated on power efficiency to provide a beyond state of the art PHY also in terms of power consumption.
The SEPHY project also has the ambition to reuse the developed PHYs for other mission critical applications. Those include automotive, avionics and industrial systems in which Ethernet is already or is likely to be the dominant networking technology. This extends the ambition of the proposal beyond space systems.
The project also includes forward looking activities to enable the future development of a Gigabit Ethernet PHY for space. This work is highly innovative and involves the use of advanced signal processing, communications and electronics (analogue and digital). Also within those studies, different standarts have been analized, such as 1000BASE-T1 or 1000BASE-CX, which will be suitable for space applications.
Additionally, a study and implementation of advanced mitigation techniques for single events effects has been done. In particular, the research of UAN on fault tolerant signal processing implementations was used to optimize the protection of the PHYs. Additionally IHP has also investigated novel mitigation techniques at architectural level to improve the overall digital implementation reliability. Finally, UAN has also investigated on power efficiency to provide a beyond state of the art PHY also in terms of power consumption.