Pilot using Independent Local & Open Technologies

Rezultaty

Collaboration roadmap and collaboration agreement with EUPEX

D35 Collaboration roadmap and collaboration agreement with EUPEX EUPEX aims at delivering a largescale modular demonstrator based on the ARMbased general purpose processor design under development in EPI In contrast the European PILOT will deliver a demonstrator based on the RISCV accelerators in EPI The European PILOT output could be integrated as an additional module into the EUPEX modular supercomputer For this reason we will define a collaboration roadmap between the two pilots to ensure the integration of the two projects into a global framework A joint Collaboration Agreement will be signed to that effect

Parallel Programming Runtimes specifications

D71 Parallel Programming Runtimes specifications BSC R PU M6 This deliverable will define the functionalities and interfaces that will have to be integrated in the Pilot Beyond the basic MPI and OpenMP support based in MPICH and the LLVM OpenMP runtime it will include the TAMPI interface for improved interoperability between MPI and OpenMP resulting in more productive mechanisms to achieve communicationcomputation overlap Also the DLB interfaces to dynamically reassign cores between OpenMP threads in different processes The document will specify the fine grain resource management policies to be implemented by these runtimes within the processes and at the node level as well as the vertical interface to the coarser grain schedulers in WP5 It will also specify the optimizations to be implemented in the internals of the runtime like vectorization offloading to communication devices as well as mechanisms to be used to minimize the impact of noise OS communications in performance

Design of AI frameworks for the Pilot platform

D61 Design of AI frameworks for the Pilot platform ETH R PU M6 This deliverable will present the design of the AI frameworks ONNXDaCe TensorFlow Tarantela for accelerated ONNXDaCe TF and distributed Tarantella learning taking into account the requirements of the respective WP1 verticals

Dissemination and Communication Plan

D21 Dissemination and Communication Plan BSC R PU M3 This deliverable will set out the dissemination and communication strategy and the activities to be undertaken to achieve it Results of the dissemination work will be reported in the periodic and final reports

Project Management and Quality Guidelines

Compilation and Emulation infrastructure

D9.1. Compilation and Emulation infrastructure (BSC, O, PU) [M9]. This deliverable will provide an updated version of the EPI compilation and Emulation infrastructure (Vehave) extended to support v1.0 of the RISC-V ISA. It will support C/C++ and will include automatic vectorization capabilities.

Publikacje

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks

Autorzy: Angelo Garofalo; Geethan Karunaratne; Francesco Conti; DAVIDE ROSSI; Irem Boybat; GIANMARCO OTTAVI; LUCA BENINI
Opublikowane w: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Numer 1, 2022, ISSN 2156-3357
Wydawca: IEEE Circuits and Systems Society
DOI: 10.1109/jetcas.2022.3170152

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters

Autorzy: Jie Chen; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi
Opublikowane w: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31 (4), Numer 8, 2023, ISSN 1557-9999
Wydawca: IEEE
DOI: 10.1109/tvlsi.2022.3228336

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Autorzy: Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti; Alfio Di Mauro; Luca Benini; Davide Rossi
Opublikowane w: IEEE Transactions on Circuits and Systems I: Regular Papers, 70 (6), Numer 8, 2023, ISSN 1558-0806
Wydawca: IEEE
DOI: 10.1109/tcsi.2023.3254810

Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training

Autorzy: Angelo Garofalo; Yvan Tortorella; Matteo Perotti; Luca Valente; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti
Opublikowane w: IEEE Open Journal of the Solid-State Circuits Society, Numer 1, 2022, ISSN 2644-1349
Wydawca: IEEE
DOI: 10.1109/ojsscs.2022.3210082

STen: An Interface for Efficient Sparsity in PyTorch

Autorzy: A. Ivanov, N. Dryden, T. Hoefler
Opublikowane w: Sparsity in Neural Networks workshop 2022, 2022
Wydawca: ETH Zurich, Scalable Parallel Computing Laboratory
DOI: 10.48550/arxiv.2304.07613

I/O-Optimal Cache-Oblivious Sparse Matrix-Sparse Matrix Multiplication

Autorzy: Niels Gleinig, Maciej Besta, Torsten Hoefler
Opublikowane w: 36th IEEE Interational Parallel and Distributed Processing Symposium, 2022, ISBN 978-1-6654-8106-9
Wydawca: 2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

The Red-Blue Pebble Game on Trees and DAGs with Large Input

Autorzy: Niels Gleinig, Torsten Hoefler
Opublikowane w: Structural Information and Communication Complexity. SIROCCO 2022, Lecture Notes in Computer Science, 2022, Strona(/y) 135-153, ISBN 978-3-031-09992-2
Wydawca: Springer, Cham
DOI: 10.1007/978-3-031-09993-9_8

Lifting C Semantics for Dataflow Optimization

Autorzy: Alexandru Calotoiu, Tal Ben-Nun,Grzegorz Kwasniewski, Johannes de Fine Licht, Timo Schneider, Philipp Schaad, Torsten Hoefler
Opublikowane w: ICS '22: Proceedings of the 36th ACM International Conference on Supercomputing, 2022
Wydawca: ICS '22: Proceedings of the 36th ACM International Conference on Supercomputing
DOI: 10.1145/3524059.3532389

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores

Autorzy: Bertaccini, Luca; Paulin, Gianna; Fischer, Tim; Mach, Stefan; Benini, Luca
Opublikowane w: 2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), Numer 5, 2022
Wydawca: IEEE
DOI: 10.1109/arith54963.2022.00010

Model-Agnostic Federated Learning

Autorzy: Gianluca Mittone; Walter Riviera; Iacopo Colonnelli; Robert Birke; Marco Aldinucci
Opublikowane w: Euro-Par 2023: Parallel Processing, Lecture Notes in Computer Science, Numer 3, 2023, Strona(/y) 383-396, ISBN 978-3-031-39698-4
Wydawca: Springer Nature
DOI: 10.1007/978-3-031-39698-4_26

Benchmarking FedAvg and FedCurv for Image Classification Tasks

Autorzy: Bruno Casella, Roberto Esposito, Carlo Cavazzoni, Marco Aldinucci
Opublikowane w: The 1st Italian Conference on Big Data and Data Science, 2022, Strona(/y) 99-100
Wydawca: CEUR-WS
DOI: 10.48550/arxiv.2303.17942

Fast Arbitrary Precision Floating Point on FPGA

Autorzy: Johannes de Fine Licht, Christopher A. Pattison, Alexandros Nikolaos Ziogas, David Simmons-Duffin, Torsten Hoefler
Opublikowane w: 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2022
Wydawca: 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
DOI: 10.1109/fccm53951.2022.9786219

Arax: A Runtime Framework for Decoupling Applications from Heterogeneous Accelerators

Autorzy: Manos Pavlidakis, Stelios Mavridis, Antony Chazapis, Giorgos Vasiliadis, and Angelos Bilas.
Opublikowane w: SoCC '22: Proceedings of the 13th Symposium on Cloud Computing, 2022, ISBN 978-1-4503-9414-7
Wydawca: Association for Computing Machinery
DOI: 10.1145/3542929.3563467

A Data-Centric Optimization Framework for Machine Learning

Autorzy: Oliver Rausch, Tal Ben-Nun, Nikoli Dryden, Andrei Ivanov, Shigang Li, Torsten Hoefler
Opublikowane w: ICS '22: Proceedings of the 36th ACM International Conference on Supercomputing, 2022, ISBN 978-1-4503-9281-5
Wydawca: Association for Computing Machinery
DOI: 10.1145/3524059.3532364

Rezultaty

Publikacje

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